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Difference between revisions of "Template:logic gate"

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| style="text-align: center; background: #ccffcc; font-size: 16px;" | '''AND Gate'''
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| style="text-align: center; background: #ccffcc; font-size: 16px;" | '''{{{name}}}'''
 
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| [[Shift register]] || [[SIPO]] || [[PISO]]
 
| [[Shift register]] || [[SIPO]] || [[PISO]]
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| [[ADC]] || [[DAC]]
 
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Revision as of 14:13, 21 November 2015


AND Gate
ANSI Symbol
and gate (ansi).svg
Functional
and gate functional.gif
Truth Table
Inputs Outputs
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
Other Gates
Buffer TriBuffer NOT
AND OR XOR
NAND NOR XNOR
Trans AOI OAI
MAJ INH IMPLY
NIMPLY
Other Components
Plexers
MUX DEMUX Encoder
Decoder Pri-Encoder
ALU
Adder Subtractor Multiplier
Divider Shifter Rotator
MAC Comparator Negator
Memory
D latch D flip-flop SR latch
JK flip-flop T flip-flop Register
Register file SRAM Counter
ROM CAM DRAM
I/O
Shift register SIPO PISO
ADC DAC 
{{logic gate
|title = AND Gate
|name = AND
}}
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