Revision as of 20:52, 7 December 2023

Exynos 8895 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2017. The processor is fabricated on Samsung's 10nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a dual-cluster configuration consisting of 4 Mongoose 2 big cores running at 2314 to 2810 MHz, 4 Cortex-A53 little cores at 1690 to 2002 MHz. This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1794 memory and incorporates a Mali-G71 MP20 GPU. The 8895 incorporates an LTE modem supporting cat 16 download and upload.

Cache

Main articles: Mongoose 2 § Cache and Cortex-A53 § Cache

For the Mongoose 2 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2x512 KiB 16-way set associative   L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 16-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-3588 Supports ECC No Max Mem 8 GiB Frequency 1800 MHz Controllers 2 Channels 2 Width 32 bit Max Bandwidth 28.64 GiB/s 29,327.36 MiB/s 30.752 GB/s 30,751.966 MB/s 0.028 TiB/s 0.0308 TB/s Bandwidth Single 14.32 GiB/s Double 28.64 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G71 Designer ARM Holdings Execution Units 20 Max Displays 2 Frequency 546 MHz 0.546 GHz 546,000 KHz Burst Frequency 850 MHz 0.85 GHz 850,000 KHz Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

All at 4K UHD 60fps.

Wireless

Wireless Communications
Cellular
4G	LTE Advanced UE Cat DL 16 (1000 Mbps) UE Cat UL 16 (280 Mbps)

ISP

• 28MP Rear
• 16MP Front
• 28MP+28MP Dual

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension Crypto Cryptographic Extension FP Floating-point Extension

Utilizing devices

• Samsung Galaxy Note 8
• Samsung Galaxy S8
• Samsung Galaxy S8+