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Difference between revisions of "amd/cores/milan"
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{{core
 
{{core
 
|name=Milan
 
|name=Milan
−
|no image=No
+
|no image=Yes
 
|developer=AMD
 
|developer=AMD
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|first announced=12th January, 2021
+
|manufacturer 2=GlobalFoundries
 +
|first announced=January 12, 2021
 +
|first launched=March 15, 2021
 
|isa=x86-64
 
|isa=x86-64
 
|microarch=Zen 3
 
|microarch=Zen 3
 
|word=64 bit
 
|word=64 bit
−
|proc=7 nm+ (TSMC N7+)
+
|proc=7 nm+
 +
|proc 2=
 
|tech=CMOS
 
|tech=CMOS
 
|package name 1=amd,socket_sp3
 
|package name 1=amd,socket_sp3
Line 18: Line 21:
 
|succession=Yes
 
|succession=Yes
 
}}
 
}}
−
'''Milan''' is codename for [[AMD]]'s high-performance enterprise-level server microprocessors based on the {{amd|Zen 3|l=arch}} microarchitecture serving as a successor to {{\\|Rome}}. Milan-based chips are set to be fabricated on TSMC's [[7 nm process]].
+
'''Milan''' is the codename of [[AMD]]'s {{amd|EPYC#7003 Series (Zen 3)|EPYC 7003 series}} of high-performance microprocessors based on the {{amd|Zen 3|l=arch}} microarchitecture for single- and dual-socket server platforms. Launched in March 2021 it succeeded the second generation of EPYC processors, the {{amd|EPYC#7002 Series (Zen 2)|EPYC 7002}} "{{\\|Rome}}" series.<ref name="pr20210315">[https://ir.amd.com/news-events/press-releases/detail/993/amd-epyc-7003-series-cpus-set-new-standard-as-highest "AMD EPYC™ 7003 Series CPUs Set New Standard as Highest Performance Server Processor"] (Press release). AMD.com. March 15, 2021. Retrieved April 2021.</ref>
  
 +
The codename "Milan" first appeared on AMD roadmaps in 2017. In 2019 a presentation leaked on YouTube and later removed revealed the basic CCD configuration.<ref>Hilgeman, Martin. "Innovator Insights: AMD Epyc for High Performance Computing Workloads". [http://www.hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php HPC-AI conference 2019], September 16, 2019.</ref> The launch of the EPYC 7003 series was announced and a 32-core model demonstrated in a keynote by AMD CEO Lisa Su on January 12, 2021 for [[wikipedia:Consumer Electronics Show|CES]] 2021.
  
−
{{future information}}
+
EPYC 7003 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 01h}} (engineering samples as Model 00h).
  
 
== Overview ==
 
== Overview ==
−
AMD Milan [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 3|l=arch}} microarchitecture. Milan is backwards platform/socket compatible with both {{\\|Naples}} and {{\\|Rome}}.
+
"Milan" development focused on microarchitectural improvements, see the {{amd|Zen 3|l=arch}} article for details. The "Milan" <abbr title="System on a Chip">SoC</abbr>s support single and 2-way multiprocessing as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and 25% more performance in the mid-stack segment compared to the prior generation.
  
−
=== Common Features ===
+
The processors are available in a 4094-contact [[land grid array]] package for {{amd|Socket SP3|l=package}} and backwards compatible with motherboards designed for "Rome" processors (EPYC "Type-1" boards) after a BIOS update. Due to limited [[wikipedia:Non-volatile memory|NVM]] capacity this update may remove support for first generation {{amd|EPYC#7001 Series (Zen)|EPYC 7001}} "{{\\|Naples}}" series CPUs. "Type-0" boards designed for the lower memory and PCIe bus frequencies of "Naples" processors are not supported.<ref name="mln-001">[https://www.amd.com/en/claims/epyc#faq-MLN-001 "AMD EPYC™ Family of Processors Claim Information"]. AMD.com. Retrieved May 2021.</ref> The codename of AMD's Type-1 reference platform is "Ethanol X".
−
{{empty section}}
+
 
 +
Like the "Rome" series, "Milan" processors are multi-chip modules containing one large I/O die and (as of May 2021) four or eight Core Complex Dies fabricated on a [[TSMC]] advanced [[7 nm process]]. <!-- Singh2020 (doi:10.1109/ISSCC19947.2020.9063113) confirms that Zen 2 is manufactured on a 7 nm process with 6-track cell library (TSMC N7 & H240 HD). Advanced process may refer to TSMC N7P or N7+. Some AMD marketing materials use "7nm+" but this cannot be construed as N7+, see e.g. https://www.anandtech.com/show/15589/amd-clarifies-comments-on-7nm-7nm-for-future-products-euv-not-specified --> The "Rome" CCD integrates two {{amd|Zen 2|l=arch}} Core Complexes (CCX), each providing four CPU cores and a shared 16 MiB L3 cache with 39 cycles average load-to-use latency. In contrast the "Milan" CCD contains a single {{amd|Zen 3|l=arch}} CCX comprising eight CPU cores (the number of usable cores varies by <abbr title="Store Keeping Unit">SKU</abbr>) which share a 32 MiB L3 cache with 46 cycles average latency, doubling the L3 capacity available to one core.
 +
 
 +
The "Milan" I/O die has largely the same features as the prior generation die fabricated on [[GlobalFoundries]]' [[14_nm_lithography_process|14 nanometer "14LPP" process]]. <!-- AMD did not disclose manufacturing details about the "Milan" sIOD. A diagram in Publ. #57091 "HPC Tuning for EPYC 7003" labels the die as "14nm". --> Apart of the memory controllers and I/O facilites described below it integrates an {{amd|secure processor|AMD Secure Processor}}, a <abbr title="System Management Unit">SMU</abbr>, <abbr title="Real Time Clock">RTC</abbr>, and other functions traditionally found in a separate chipset.
 +
 
 +
In an interview on March 15, 2021 AMD SVP Forrest Norrod confirmed plans for another server processor series based on the Zen 3 microarchitecture with the codename "Trento". These processors will use a different I/O die with additional coherent {{amd|Infinity Fabric}} links to attach accelerators. They will be used in the exaflop [[wikipedia:Frontier_%28supercomputer%29|Frontier]] supercomputer with nodes comprising one EPYC CPU and four Radeon Instinct MI200 GPUs.<ref>"[https://www.anandtech.com/show/16548/interview-with-amd-forrest-norrod-milan The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod]. anandtech.com. Retrieved May 2021.</ref> "Milan" processors will power the 100 petaflop [[wikipedia:Perlmutter_%28supercomputer%29|Perlmutter]] supercomputer, [https://news.iu.edu/stories/2020/06/iub/releases/01-jetstream-cloud-computing-awarded-nsf-grant.html Jetstream 2], [https://www.rcac.purdue.edu/compute/anvil/ Anvil], and a yet-to-be-named HPE Cray EX system at NSCC Singapore.
 +
 
 +
=== Memory Interface ===
 +
The "Milan" I/O die integrates eight [[wikipedia:DDR4 SDRAM|DDR4]] memory controllers (<abbr title="Unified Memory Controller">UMC</abbr>s), two per I/O die quadrant, which achieve data rates from 1333 to 3200 MT/s.<ref name="amd-55898">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref> Up to 2 DIMMs per channel are supported. The {{amd|Infinity Fabric}} and memory bus clock can be coupled to slightly reduce the memory latency, "Milan" processors permit this up to 1600 MHz matching DDR4-3200 memory.<ref name="amd-57091">{{cite techdoc|title=High Performance Computing (HPC) Tuning Guide for AMD EPYC™ 7003 Series Processors|url=https://www.amd.com/system/files/documents/high-performance-computing-tuning-guide-amd-epyc7003-series-processors.pdf|publ=AMD|pid=57091|rev=2.0|date=2021-03}}</ref> The memory controllers support [[wikipedia:ECC memory|ECC memory]] and the following DIMM types:<ref name="amd-56873">{{cite techdoc|title=Memory Population Guidelines for AMD EPYC™ 7003 Series Processors|publ=AMD|pid=56873|rev=0.70|date=2020-11}}</ref>
 +
 
 +
* <abbr title="Single Rank">SR</abbr>/<abbr title="Dual Rank">DR</abbr> [[wikipedia:Registered memory|RDIMM]] built with x4 and x8 DDR4 devices
 +
* <abbr title="Quad Rank">4R</abbr>/<abbr title="Eight Rank">8R</abbr> [[wikipedia:Registered memory|LRDIMM]] built with x4 devices (<abbr title="Quad Rank, two dies">4DR</abbr>, <abbr title="Quad Rank = Dual Rank × 2 dies stacked">2S2R</abbr>, <abbr title="Eight Rank = Dual Rank × 4 dies stacked">2S4R</abbr>)
 +
* 4R/8R [[3DS DIMM]] built with x4 devices (2S2R, 2S4R)
 +
* [[wikipedia:NVDIMM|NVDIMM-N]] (DRAM with NVM backup) 
 +
 
 +
The maximum total memory capacity is 4 TiB per socket using 16 LRDIMMs or 3DS DIMMs of 256 GiB capacity.
 +
 
 +
{| class="wikitable" style="display: inline-table; text-align: center;"
 +
! colspan="4" | Memory speed based on DIMM population
 +
|-
 +
! rowspan="2" | DIMM Type || colspan="2" | DIMM Population/Channel || rowspan="2" | Max. Data Rate<br/>(MT/s)
 +
|-
 +
! DIMM0 || DIMM1
 +
|-
 +
| rowspan="5" | RDIMM || - || 1R || 3200
 +
|-
 +
| - || 2R or 2DR || 3200
 +
|-
 +
| 1R || 1R || 2933
 +
|-
 +
| 1R || 2R or 2DR || 2933
 +
|-
 +
| 2R or 2DR || 2R or 2DR || 2933
 +
|-
 +
| rowspan="6" | LRDIMM || – || 4DR || 3200
 +
|-
 +
| – || 2S2R (4 ranks) || 3200
 +
|-
 +
| – || 2S4R (8 ranks) || 3200
 +
|-
 +
| 4DR || 4DR || 2933
 +
|-
 +
| 2S2R (4 ranks) || 2S2R (4 ranks) || 2933
 +
|-
 +
| 2S4R (8 ranks) || 2S4R (8 ranks) || 2933
 +
|-
 +
| rowspan="4" | 3DS || – || 2S2R (4 ranks) || 2933
 +
|-
 +
| – || 2S4R (8 ranks) || 2933
 +
|-
 +
| 2S2R (4 ranks) || 2S2R (4 ranks) || 2666
 +
|-
 +
| 2S4R (8 ranks) || 2S4R (8 ranks) || 2666
 +
|}
 +
DIMM0 is the module closer to the CPU. This socket is not present on motherboards which support only one DIMM per channel.
 +
 
 +
The memory channels are designated A to H. "Rome" and "Milan" processors support 2-, 4-, 8-, and 16-way (on 2P systems) memory interleaving. 4-way mode interleaves the memory channels ABCD and/or EFGH, or CDGH if only these four channels are populated. In contrast to the prior generation CDGH interleaving is supported by all EPYC 7003 <abbr title="Stock Keeping Unit">SKU</abbr>s with 128 MiB L3 cache or less, none having only two <abbr title="Core Complex Die">CCD</abbr>s. Additionally all "Milan" processors support 6-way interleaving if channels B and F remain unpopulated, with a maximum of 256 GiB capacity per channel and restricted to 2 or 4 KiB interleaving size.<ref name="amd-56873"/> The new options enable balanced memory utilization at reduced memory cost when peak memory performance is not required.
 +
 
 +
With all UMCs implemented in a central I/O die "Rome" and "Milan" processors have a single [[wikipedia:Non-uniform memory access|NUMA]] domain per socket and two NUMA distances on dual-socket platforms. AMD advertised a flatter NUMA domain and reduced inter-core latency since the <abbr title="Core Complex">CCX</abbr>s were pairwise united and the CPU cores in a CCX can exchange data through the shared L3 cache rather than the {{amd|Infinity Fabric|Scalable Data Fabric}} on the I/O die. "Milan" still supports the ''NUMA Nodes Per Socket'' (NPS) and ''<abbr title="Last Level Cache">LLC</abbr>/L3/CCX as NUMA domain'' BIOS setup options. 6-way memory interleaving is only possible with NPS=1.<ref name="amd-56873"/>
 +
 
 +
Finally an unspecified [[probe filter]] improvement was advertised.
 +
 
 +
=== Input/Output Interfaces ===
 +
The "Milan" I/O die integrates eight 16-lane [[wikipedia:PCI Express|PCIe]] Gen 4 (16 GT/s) controllers. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links. Each controller supports up to eight PCIe links. On dual-socket systems four, or optionally three, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these <abbr title="External Global Memory Interconnect, 2nd generation">xGMI-2</abbr> links can reach 18 GT/s. The I/O die also integrates four [[wikipedia:Serial ATA|SATA]] 3.0 (6 Gb/s) controllers which support up to eight links each, multiplexed with the lower eight lanes of four x16 links. [[wikipedia:NVM Express|NVMe]] devices are supported as well. An additional 2-lane PCIe Gen 2 controller powers the WAFL links. One or both of these lanes serve as {{amd|Infinity Fabric#Scalable Control Fabric (SCF)|SCF}} links between sockets and are otherwise available for I/O, e.g. to attach a [[wikipedia:Intelligent Platform Management Interface#Baseboard management controller|BMC]]. In sum up to 128 + 2 PCIe lanes are available per socket and up to 2 × 80 + 2 × 1 = 162 lanes total on dual-socket platforms.<ref name="amd-55898"/>
 +
 
 +
With the "Milan" series the integrated <abbr title="Input/Output Memory Management Unit">IOMMU</abbr>s were optimized to better handle high-bandwidth devices such as 200 Gbps Ethernet adapters. Support for hotplug surprise removal was brought up to current [[wikipedia:PCI-SIG|PCI-SIG]] implementation guidelines.
 +
 
 +
Four USB 1.1/2.0/3.1 (10 Gb/s) ports are available on the CPU package, and several low-speed interfaces listed below.
 +
 
 +
=== Feature Summary ===
 +
All "Milan" processors have the following features:
 +
 
 +
* 8 to 64 {{amd|Zen 3|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]
 +
** 4,096-entry Op cache, 2 × 32 KiB L1, and 512 KiB L2 cache per core
 +
** x86 extensions ('''new'''):    {{x86|ABM}}, {{x86|ADX}}, {{x86|AES}}, {{x86|AVX}}, {{x86|AVX2}},  {{x86|BMI1}}, {{x86|BMI2}},  {{x86|CLFLUSH}}, {{x86|CLFLUSHOPT}}, {{x86|CLWB}}, {{x86|CLZERO}}, {{x86|CMOV}}, {{x86|CMPXCHG8B}}, {{x86|CMPXCHG16B}},  {{x86|EMMX}}, {{x86|F16C}},  {{x86|FMA3}},  {{x86|FPU}}, {{x86|FSGSBASE}}, {{x86|FXSR}}, '''{{x86|INVLPGB}}''', '''{{x86|INVPCID}}''', {{x86|LahfSahf}},  {{x86|MCOMMIT}}, {{x86|MMX}},  {{x86|MONITOR}}, {{x86|MONITORX}}, {{x86|MOVBE}}, {{x86|MSR}},  {{x86|PCLMULQDQ}}, '''{{x86|PKU}}''', {{x86|POPCNT}}, {{x86|PREFETCH}}, {{x86|RDPID}}, {{x86|RDPRU}}, {{x86|RDRAND}}, {{x86|RDTSCP}}, {{x86|RDSEED}},  {{x86|SHA}},    {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4A}},  {{x86|SSE4.1}}, {{x86|SSE4.2}},  {{x86|SysCallSysRet}}, {{x86|SysEnterSysExit}},  {{x86|TSC}}, '''{{x86|VAES}}''', '''{{x86|VPCLMULQDQ}}''', {{x86|WBNOINVD}},    {{x86|XSAVE}}, {{x86|XSAVEC}}, {{x86|XSAVEOPT}}
 +
** Security extensions: '''{{x86|CET|CET_SS}}''', {{x86|GMET}}, {{x86|NX}}, {{x86|SME|SEV}}, {{x86|SME|SEV-ES}}, '''{{x86|SME|SEV-SNP}}''', {{x86|SMAP}}, {{x86|SME|SME/TSME}}, {{x86|SMEP}}, {{x86|UMIP}}
 +
** Speculation control: {{x86|IBPB}}, {{x86|IBRS}}, '''{{x86|PSFD}}''', {{x86|SSBD}}, {{x86|STIBP}}
 +
* Up to 32 MiB L3 cache per Core Complex (up to 8 CPU cores), 64 to 256 MiB total
 +
 
 +
* 8 × 64/72 bit DDR4 SDRAM interface up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s
 +
** Up to 2 DIMMs per channel, 16 total
 +
** SR/DR RDIMMs, 4R/8R LRDIMMs, 3DS DIMMs, NVDIMMs type N
 +
** SEC-DED ECC support
 +
** Up to 4 TiB total
 +
 
 +
* Eight 16-lane PCIe Gen 4 (16 GT/s) controllers
 +
** Configurable x16, x8, x4, x2, x1
 +
** Up to 8 links per controller
 +
** SATA, xGMI function on some lanes
 +
* One 2-lane PCIe Gen 2 controller (WAFL)
 +
* Four SATA 3.0 (6 Gb/s) controllers, up to 8 lanes each
 +
* Four USB 1.1/2.0/3.1 (10 Gb/s) ports
 +
* [[wikipedia:SD card|SD interface]], 6 × [[wikipedia:I%C2%B2C|I2C]], 2 × [[wikipedia:System Management Bus|SMBus]], [[wikipedia:Low Pin Count|LPC]] interface, 4 × [[wikipedia:Universal asynchronous receiver transmitter|UART]], [[wikipedia:Serial Peripheral Interface|SPI/eSPI]], [[wikipedia:General-purpose input/output|GPIO]]
 +
 
 +
* {{amd|secure processor|AMD Secure Processor}}, [[Secure Boot]], Hardware root-of-trust
 +
 
 +
* TDP range 155 to 280 Watt, configurable
 +
 
 +
=== Naming Scheme ===
 +
{{chip identification
 +
| title    =
 +
| parts    = 6
 +
| ex 1      = EPYC&nbsp;
 +
| ex 2      = 7
 +
| ex 3      = 5
 +
| ex 4      = 5
 +
| ex 5      = 3
 +
| ex 6      = P
 +
| desc 1    = '''Product Family'''
 +
| desc 2    = <table style="text-align:left"><th colspan="2">Product Series</th>
 +
<tr><th>7xxx</th><td>High-performance server CPU/SOC</td></tr></table>
 +
| desc 3    = <table style="text-align:left">
 +
<th colspan="2">Product Model (Core Count)</th>
 +
<tr><th>2</th><td>8 cores</td></tr>
 +
<tr><th>3</th><td>16</td></tr>
 +
<tr><th>4</th><td>24-28</td></tr>
 +
<tr><th>5</th><td>32</td></tr>
 +
<tr><th>6</th><td>40-56</td></tr>
 +
<tr><th>7</th><td>64 cores</td></tr></table>
 +
| desc 4    = <table style="text-align:left">
 +
<th colspan="2">Performance Level</th>
 +
<tr><th>1</th><td>Value</td></tr>
 +
<tr><th>4, 5, 6</th><td>Performance</td></tr>
 +
<tr><th>F</th><td>Frequency optimized and high cache/core ratio,<br/>high performance per core</td></tr></table>
 +
| desc 5    = <table style="text-align:left">
 +
<th colspan="2">Generation</th>
 +
<tr><th>3</th><td>Third generation, 7003 "Milan" series</td></tr></table>
 +
| desc 6    = <table style="text-align:left">
 +
<th colspan="2">Feature Modifier</th>
 +
<tr><th>(none)</th><td>1P, 2P</td></tr>
 +
<tr><th>P</th><td>1P (single socket) only</td></tr></table>
 +
}}
 +
 
 +
== Milan Processors ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc5 tc6">
 +
{{comp table header|main|10:List of Milan Processors}}
 +
{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
 +
{{comp table header|lsep|25:[[Uniprocessors]]}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[max cpu count::1]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|format=template
 +
|template=proc table 3
 +
|userparam=12
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[max cpu count::>>1]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|format=template
 +
|template=proc table 3
 +
|userparam=12
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table header|lsep|25:Frequency-optimized SKUs}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]] [[part of::Frequency-optimized SKUs]]
 +
|?full page name
 +
|?model number
 +
|?microprocessor family
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|format=template
 +
|template=proc table 3
 +
|userparam=12
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Milan]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
=== SKU Comparison ===
 +
Below are a number of SKU comparison graphs based on their specifications.
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
 +
|?core count
 +
|?base frequency
 +
|charttitle=Cores vs. Base Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
 +
|?core count
 +
|?turbo frequency
 +
|charttitle=Cores vs. Turbo Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
 +
|?core count
 +
|?tdp
 +
|charttitle=Cores vs. TDP
 +
|numbersaxislabel=TDP (W)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by amd]] [[core name::Milan]]
 +
|?turbo frequency
 +
|?tdp
 +
|charttitle=Frequency vs. TDP
 +
|numbersaxislabel=TDP (W)
 +
|labelaxislabel=Frequency (MHz)
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
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|format=jqplotseries
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|mainlabel=-
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}}
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</div>
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 +
{{clear}}
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 +
== References ==
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<references/>
 +
 
 +
== See also ==
 +
{{amd zen 3 core see also}}

Latest revision as of 00:26, 31 May 2021

Edit Values
Milan
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
IntroductionJanuary 12, 2021 (announced)
March 15, 2021 (launched)
Microarchitecture
ISAx86-64
MicroarchitectureZen 3
Word Size
8 octets
16 nibbles
64 bit
Process7 nm+
"nm+" is not declared as a valid unit of measurement for this property.
TechnologyCMOS
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm
7.54 cm
2.969 in
× 58.5 mm
5.85 cm
2.303 in
× 6.26 mm
0.246 in
Pitch0.87 mm
0.0343 in
× 1 mm
0.0394 in
Contacts4094
SocketSP3, LGA-4094
Succession

Milan is the codename of AMD's EPYC 7003 series of high-performance microprocessors based on the Zen 3 microarchitecture for single- and dual-socket server platforms. Launched in March 2021 it succeeded the second generation of EPYC processors, the EPYC 7002 "Rome" series.[1]

The codename "Milan" first appeared on AMD roadmaps in 2017. In 2019 a presentation leaked on YouTube and later removed revealed the basic CCD configuration.[2] The launch of the EPYC 7003 series was announced and a 32-core model demonstrated in a keynote by AMD CEO Lisa Su on January 12, 2021 for CES 2021.

EPYC 7003 processors identify as members of AMD CPU Family 19h, Model 01h (engineering samples as Model 00h).

Overview[edit]

"Milan" development focused on microarchitectural improvements, see the Zen 3 article for details. The "Milan" SoCs support single and 2-way multiprocessing as well as 2-way multithreading with up to 64 cores and 128 threads per processor. AMD claims up to 15% better performance per cost and 25% more performance in the mid-stack segment compared to the prior generation.

The processors are available in a 4094-contact land grid array package for Socket SP3 and backwards compatible with motherboards designed for "Rome" processors (EPYC "Type-1" boards) after a BIOS update. Due to limited NVM capacity this update may remove support for first generation EPYC 7001 "Naples" series CPUs. "Type-0" boards designed for the lower memory and PCIe bus frequencies of "Naples" processors are not supported.[3] The codename of AMD's Type-1 reference platform is "Ethanol X".

Like the "Rome" series, "Milan" processors are multi-chip modules containing one large I/O die and (as of May 2021) four or eight Core Complex Dies fabricated on a TSMC advanced 7 nm process. The "Rome" CCD integrates two Zen 2 Core Complexes (CCX), each providing four CPU cores and a shared 16 MiB L3 cache with 39 cycles average load-to-use latency. In contrast the "Milan" CCD contains a single Zen 3 CCX comprising eight CPU cores (the number of usable cores varies by SKU) which share a 32 MiB L3 cache with 46 cycles average latency, doubling the L3 capacity available to one core.

The "Milan" I/O die has largely the same features as the prior generation die fabricated on GlobalFoundries' 14 nanometer "14LPP" process. Apart of the memory controllers and I/O facilites described below it integrates an AMD Secure Processor, a SMU, RTC, and other functions traditionally found in a separate chipset.

In an interview on March 15, 2021 AMD SVP Forrest Norrod confirmed plans for another server processor series based on the Zen 3 microarchitecture with the codename "Trento". These processors will use a different I/O die with additional coherent Infinity Fabric links to attach accelerators. They will be used in the exaflop Frontier supercomputer with nodes comprising one EPYC CPU and four Radeon Instinct MI200 GPUs.[4] "Milan" processors will power the 100 petaflop Perlmutter supercomputer, Jetstream 2, Anvil, and a yet-to-be-named HPE Cray EX system at NSCC Singapore.

Memory Interface[edit]

The "Milan" I/O die integrates eight DDR4 memory controllers (UMCs), two per I/O die quadrant, which achieve data rates from 1333 to 3200 MT/s.[5] Up to 2 DIMMs per channel are supported. The Infinity Fabric and memory bus clock can be coupled to slightly reduce the memory latency, "Milan" processors permit this up to 1600 MHz matching DDR4-3200 memory.[6] The memory controllers support ECC memory and the following DIMM types:[7]

  • SR/DR RDIMM built with x4 and x8 DDR4 devices
  • 4R/8R LRDIMM built with x4 devices (4DR, 2S2R, 2S4R)
  • 4R/8R 3DS DIMM built with x4 devices (2S2R, 2S4R)
  • NVDIMM-N (DRAM with NVM backup)

The maximum total memory capacity is 4 TiB per socket using 16 LRDIMMs or 3DS DIMMs of 256 GiB capacity.

Memory speed based on DIMM population
DIMM Type DIMM Population/Channel Max. Data Rate
(MT/s)
DIMM0 DIMM1
RDIMM - 1R 3200
- 2R or 2DR 3200
1R 1R 2933
1R 2R or 2DR 2933
2R or 2DR 2R or 2DR 2933
LRDIMM – 4DR 3200
– 2S2R (4 ranks) 3200
– 2S4R (8 ranks) 3200
4DR 4DR 2933
2S2R (4 ranks) 2S2R (4 ranks) 2933
2S4R (8 ranks) 2S4R (8 ranks) 2933
3DS – 2S2R (4 ranks) 2933
– 2S4R (8 ranks) 2933
2S2R (4 ranks) 2S2R (4 ranks) 2666
2S4R (8 ranks) 2S4R (8 ranks) 2666

DIMM0 is the module closer to the CPU. This socket is not present on motherboards which support only one DIMM per channel.

The memory channels are designated A to H. "Rome" and "Milan" processors support 2-, 4-, 8-, and 16-way (on 2P systems) memory interleaving. 4-way mode interleaves the memory channels ABCD and/or EFGH, or CDGH if only these four channels are populated. In contrast to the prior generation CDGH interleaving is supported by all EPYC 7003 SKUs with 128 MiB L3 cache or less, none having only two CCDs. Additionally all "Milan" processors support 6-way interleaving if channels B and F remain unpopulated, with a maximum of 256 GiB capacity per channel and restricted to 2 or 4 KiB interleaving size.[7] The new options enable balanced memory utilization at reduced memory cost when peak memory performance is not required.

With all UMCs implemented in a central I/O die "Rome" and "Milan" processors have a single NUMA domain per socket and two NUMA distances on dual-socket platforms. AMD advertised a flatter NUMA domain and reduced inter-core latency since the CCXs were pairwise united and the CPU cores in a CCX can exchange data through the shared L3 cache rather than the Scalable Data Fabric on the I/O die. "Milan" still supports the NUMA Nodes Per Socket (NPS) and LLC/L3/CCX as NUMA domain BIOS setup options. 6-way memory interleaving is only possible with NPS=1.[7]

Finally an unspecified probe filter improvement was advertised.

Input/Output Interfaces[edit]

The "Milan" I/O die integrates eight 16-lane PCIe Gen 4 (16 GT/s) controllers. Link bifurcation permits configuration of the PCIe lanes as x16, x8, x4, x2, or x1 wide independent links. Each controller supports up to eight PCIe links. On dual-socket systems four, or optionally three, x16 links are repurposed for cache coherent inter-socket traffic. The raw data rate of these xGMI-2 links can reach 18 GT/s. The I/O die also integrates four SATA 3.0 (6 Gb/s) controllers which support up to eight links each, multiplexed with the lower eight lanes of four x16 links. NVMe devices are supported as well. An additional 2-lane PCIe Gen 2 controller powers the WAFL links. One or both of these lanes serve as SCF links between sockets and are otherwise available for I/O, e.g. to attach a BMC. In sum up to 128 + 2 PCIe lanes are available per socket and up to 2 × 80 + 2 × 1 = 162 lanes total on dual-socket platforms.[5]

With the "Milan" series the integrated IOMMUs were optimized to better handle high-bandwidth devices such as 200 Gbps Ethernet adapters. Support for hotplug surprise removal was brought up to current PCI-SIG implementation guidelines.

Four USB 1.1/2.0/3.1 (10 Gb/s) ports are available on the CPU package, and several low-speed interfaces listed below.

Feature Summary[edit]

All "Milan" processors have the following features:

  • 8 × 64/72 bit DDR4 SDRAM interface up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s
    • Up to 2 DIMMs per channel, 16 total
    • SR/DR RDIMMs, 4R/8R LRDIMMs, 3DS DIMMs, NVDIMMs type N
    • SEC-DED ECC support
    • Up to 4 TiB total
  • Eight 16-lane PCIe Gen 4 (16 GT/s) controllers
    • Configurable x16, x8, x4, x2, x1
    • Up to 8 links per controller
    • SATA, xGMI function on some lanes
  • One 2-lane PCIe Gen 2 controller (WAFL)
  • Four SATA 3.0 (6 Gb/s) controllers, up to 8 lanes each
  • Four USB 1.1/2.0/3.1 (10 Gb/s) ports
  • SD interface, 6 × I2C, 2 × SMBus, LPC interface, 4 × UART, SPI/eSPI, GPIO
  • TDP range 155 to 280 Watt, configurable

Naming Scheme[edit]

EPYC 7553P 
      
Feature Modifier
(none)1P, 2P
P1P (single socket) only
     
Generation
3Third generation, 7003 "Milan" series
    
Performance Level
1Value
4, 5, 6Performance
FFrequency optimized and high cache/core ratio,
high performance per core
   
Product Model (Core Count)
28 cores
316
424-28
532
640-56
764 cores
  
Product Series
7xxxHigh-performance server CPU/SOC
 Product Family

Milan Processors[edit]

 List of Milan Processors
ModelFamilyPriceLaunchedCoresThreadsTDPL2$L3$BaseTurbo
 Uniprocessors
7313PEPYC$ 913.00
€ 821.70
£ 739.53
¥ 94,340.29
15 March 20211632155 W
155,000 mW
0.208 hp
0.155 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
7443PEPYC$ 1,337.00
€ 1,203.30
£ 1,082.97
¥ 138,152.21
15 March 20212448200 W
200,000 mW
0.268 hp
0.2 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.85 GHz
2,850 MHz
2,850,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
7543PEPYC$ 2,730.00
€ 2,457.00
£ 2,211.30
¥ 282,090.90
15 March 20213264225 W
225,000 mW
0.302 hp
0.225 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
7713PEPYC$ 5,010.00
€ 4,509.00
£ 4,058.10
¥ 517,683.30
15 March 202164128225 W
225,000 mW
0.302 hp
0.225 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3.675 GHz
3,675 MHz
3,675,000 kHz
 Multiprocessors (dual-socket)
72F3EPYC$ 2,468.00
€ 2,221.20
£ 1,999.08
¥ 255,018.44
15 March 2021816180 W
180,000 mW
0.241 hp
0.18 kW
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
7313EPYC$ 1,083.00
€ 974.70
£ 877.23
¥ 111,906.39
15 March 20211632155 W
155,000 mW
0.208 hp
0.155 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3 GHz
3,000 MHz
3,000,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
7343EPYC$ 1,565.00
€ 1,408.50
£ 1,267.65
¥ 161,711.45
15 March 20211632190 W
190,000 mW
0.255 hp
0.19 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.2 GHz
3,200 MHz
3,200,000 kHz
3.9 GHz
3,900 MHz
3,900,000 kHz
73F3EPYC$ 3,521.00
€ 3,168.90
£ 2,852.01
¥ 363,824.93
15 March 20211632240 W
240,000 mW
0.322 hp
0.24 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.5 GHz
3,500 MHz
3,500,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
7413EPYC$ 1,825.00
€ 1,642.50
£ 1,478.25
¥ 188,577.25
15 March 20212448180 W
180,000 mW
0.241 hp
0.18 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.65 GHz
2,650 MHz
2,650,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
7443EPYC$ 2,010.00
€ 1,809.00
£ 1,628.10
¥ 207,693.30
15 March 20212448200 W
200,000 mW
0.268 hp
0.2 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.85 GHz
2,850 MHz
2,850,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
7453EPYC$ 1,570.00
€ 1,413.00
£ 1,271.70
¥ 162,228.10
15 March 20212856225 W
225,000 mW
0.302 hp
0.225 kW
14 MiB
14,336 KiB
14,680,064 B
0.0137 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
2.75 GHz
2,750 MHz
2,750,000 kHz
3.45 GHz
3,450 MHz
3,450,000 kHz
74F3EPYC$ 2,900.00
€ 2,610.00
£ 2,349.00
¥ 299,657.00
15 March 20212448240 W
240,000 mW
0.322 hp
0.24 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.2 GHz
3,200 MHz
3,200,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
7513EPYC$ 2,840.00
€ 2,556.00
£ 2,300.40
¥ 293,457.20
15 March 20213264200 W
200,000 mW
0.268 hp
0.2 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
3.65 GHz
3,650 MHz
3,650,000 kHz
7543EPYC$ 3,761.00
€ 3,384.90
£ 3,046.41
¥ 388,624.13
15 March 20213264225 W
225,000 mW
0.302 hp
0.225 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.8 GHz
2,800 MHz
2,800,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
75F3EPYC$ 4,860.00
€ 4,374.00
£ 3,936.60
¥ 502,183.80
15 March 20213264280 W
280,000 mW
0.375 hp
0.28 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.95 GHz
2,950 MHz
2,950,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
7643EPYC$ 4,995.00
€ 4,495.50
£ 4,045.95
¥ 516,133.35
15 March 20214896225 W
225,000 mW
0.302 hp
0.225 kW
24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.3 GHz
2,300 MHz
2,300,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
7663EPYC$ 6,366.00
€ 5,729.40
£ 5,156.46
¥ 657,798.78
15 March 202156112240 W
240,000 mW
0.322 hp
0.24 kW
28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
7713EPYC$ 7,060.00
€ 6,354.00
£ 5,718.60
¥ 729,509.80
15 March 202164128225 W
225,000 mW
0.302 hp
0.225 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3.675 GHz
3,675 MHz
3,675,000 kHz
7763EPYC$ 7,890.00
€ 7,101.00
£ 6,390.90
¥ 815,273.70
15 March 202164128280 W
280,000 mW
0.375 hp
0.28 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.45 GHz
2,450 MHz
2,450,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
 Frequency-optimized SKUs
72F3EPYC$ 2,468.00
€ 2,221.20
£ 1,999.08
¥ 255,018.44
15 March 2021816180 W
180,000 mW
0.241 hp
0.18 kW
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.1 GHz
4,100 MHz
4,100,000 kHz
73F3EPYC$ 3,521.00
€ 3,168.90
£ 2,852.01
¥ 363,824.93
15 March 20211632240 W
240,000 mW
0.322 hp
0.24 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.5 GHz
3,500 MHz
3,500,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
74F3EPYC$ 2,900.00
€ 2,610.00
£ 2,349.00
¥ 299,657.00
15 March 20212448240 W
240,000 mW
0.322 hp
0.24 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
3.2 GHz
3,200 MHz
3,200,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
75F3EPYC$ 4,860.00
€ 4,374.00
£ 3,936.60
¥ 502,183.80
15 March 20213264280 W
280,000 mW
0.375 hp
0.28 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.95 GHz
2,950 MHz
2,950,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
Count: 19

SKU Comparison[edit]

Below are a number of SKU comparison graphs based on their specifications.

References[edit]

  1. ↑ "AMD EPYC™ 7003 Series CPUs Set New Standard as Highest Performance Server Processor" (Press release). AMD.com. March 15, 2021. Retrieved April 2021.
  2. ↑ Hilgeman, Martin. "Innovator Insights: AMD Epyc for High Performance Computing Workloads". HPC-AI conference 2019, September 16, 2019.
  3. ↑ "AMD EPYC™ Family of Processors Claim Information". AMD.com. Retrieved May 2021.
  4. ↑ "The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod. anandtech.com. Retrieved May 2021.
  5. ↑ 5.0 5.1 "Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors", AMD Publ. #55898, Rev. 0.35, February 5, 2021
  6. ↑ "High Performance Computing (HPC) Tuning Guide for AMD EPYC™ 7003 Series Processors", AMD Publ. #57091, Rev. 2.0, March 2021
  7. ↑ 7.0 7.1 7.2 "Memory Population Guidelines for AMD EPYC™ 7003 Series Processors", AMD Publ. #56873, Rev. 0.70, November 2020

See also[edit]

arrow up 1.svgPower/Performance

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/cores/milan&oldid=98985"
Facts about "Milan - Cores - AMD"
RDF feed
designerAMD +
first announcedJanuary 12, 2021 +
first launchedMarch 15, 2021 +
instance ofcore +
isax86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 3 +
nameMilan +
packageSP3 + and FCLGA-4094 +
socketSP3 + and LGA-4094 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +