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Difference between revisions of "intel/microarchitectures/tiger lake"
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(→‎Key changes from {{\\|Ice Lake}})
 
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|introduction=September 2, 2020
 
|introduction=September 2, 2020
 
|process=10 nm
 
|process=10 nm
 +
|cores=2
 +
|cores 2=4
 +
|cores 3=6
 +
|cores 4=8
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages min=14
 +
|stages max=19
 +
|decode=5-way
 
|isa=x86-64
 
|isa=x86-64
 +
|l1i=32 KiB
 +
|l1i per=core
 +
|l1i desc=8-way set associative
 +
|l1d=48 KiB
 +
|l1d per=core
 +
|l1d desc=12-way set associative
 +
|l2=1280 KiB
 +
|l2 per=core
 +
|l2 desc=20-way set associative
 +
|l3=3 MiB
 +
|l3 per=core
 +
|l3 desc=12-way set associative
 
|core name=Tiger Lake U
 
|core name=Tiger Lake U
 
|core name 2=Tiger Lake H
 
|core name 2=Tiger Lake H
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| {{intel|Tiger Lake H35|l=core}} || TGL-H35 || High-performance Graphics || || 35W TDP. High mobile performance, mobile workstations
 
| {{intel|Tiger Lake H35|l=core}} || TGL-H35 || High-performance Graphics || || 35W TDP. High mobile performance, mobile workstations
 
|-
 
|-
−
| {{intel|Tiger Lake H45|l=core}} || TGL-H45 || High-performance Graphics || || 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations
+
| {{intel|Tiger Lake H|l=core}} || TGL-H || High-performance Graphics || || 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations
 
|}
 
|}
  
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* Core
 
* Core
 
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}
 
** {{\\|Sunny Cove}} '''➡''' {{\\|Willow Cove}}
 +
*** Implemented POP to PUSH data forwarding, reg->reg and imm->reg (~1 PUSH+POP pair per cycle)
 
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
 
** Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
 
** 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
 
** 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core

Latest revision as of 09:46, 19 July 2023

Edit Values
Tiger Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionSeptember 2, 2020
Process10 nm
Core Configs2, 4, 6, 8
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache48 KiB/core
12-way set associative
L2 Cache1280 KiB/core
20-way set associative
L3 Cache3 MiB/core
12-way set associative
Cores
Core NamesTiger Lake U,
Tiger Lake H
Succession
Contemporary
Sapphire Rapids
Rocket Lake

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames[edit]

Core Abbrev Description Graphics Target
Tiger Lake Y TGL-Y Extremely low power 2-in-1s detachable, tablets, and computer sticks
Tiger Lake U TGL-U Ultra-low Power Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Tiger Lake H35 TGL-H35 High-performance Graphics 35W TDP. High mobile performance, mobile workstations
Tiger Lake H TGL-H High-performance Graphics 45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations

Process Technology[edit]

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.

History[edit]

Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.

Architecture[edit]

Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake[edit]

  • Core
    • Sunny Cove ➡ Willow Cove
      • Implemented POP to PUSH data forwarding, reg->reg and imm->reg (~1 PUSH+POP pair per cycle)
    • Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
    • 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
  • GPU
    • Gen11 ➡ Gen12 (Xe)
    • 1.5x more EUs (96, up from 64)
  • Display
    • HDMI 2.1 (from HDMI 2.0b)
  • I/O
    • PCIe 4.0 (from 3.0)
  • Hardware Telemetry
    • Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.
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Facts about "Tiger Lake - Microarchitectures - Intel"
RDF feed
codenameTiger Lake +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launchedSeptember 2, 2020 +
full page nameintel/microarchitectures/tiger lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTiger Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +