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Difference between revisions of "intel/xeon silver/4215r"
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|first launched=February 24, 2020 | |first launched=February 24, 2020 | ||
|release price (tray)=$794.00 | |release price (tray)=$794.00 | ||
+ | |S-Spec=SRGZE | ||
|family=Xeon Silver | |family=Xeon Silver | ||
|series=4200 | |series=4200 | ||
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|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
− | |core name=Cascade Lake | + | |core name=Cascade Lake R |
|core family=6 | |core family=6 | ||
|process=14 nm | |process=14 nm | ||
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|predecessor link=intel/xeon silver/4215 | |predecessor link=intel/xeon silver/4215 | ||
}} | }} | ||
− | '''Xeon Silver 4215R''' is a {{arch|64}} [[ | + | '''Xeon Silver 4215R''' is a {{arch|64}} [[8-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Silver 4215R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 3.2 GHz with a TDP of 130 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz. |
== Cache == | == Cache == | ||
Line 192: | Line 193: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,200MHz | ||
+ | |freq_1=4,000MHz | ||
+ | |freq_2=4,000MHz | ||
+ | |freq_3=3,800MHz | ||
+ | |freq_4=3,800MHz | ||
+ | |freq_5=3,600MHz | ||
+ | |freq_6=3,600MHz | ||
+ | |freq_7=3,600MHz | ||
+ | |freq_8=3,600MHz | ||
+ | |freq_avx2_base=2,000MHz | ||
+ | |freq_avx2_1=3,600MHz | ||
+ | |freq_avx2_2=3,600MHz | ||
+ | |freq_avx2_3=3,300MHz | ||
+ | |freq_avx2_4=3,300MHz | ||
+ | |freq_avx2_5=2,600MHz | ||
+ | |freq_avx2_6=2,600MHz | ||
+ | |freq_avx2_7=2,600MHz | ||
+ | |freq_avx2_8=2,600MHz | ||
+ | |freq_avx512_base=1,500MHz | ||
+ | |freq_avx512_1=3,300MHz | ||
+ | |freq_avx512_2=3,300MHz | ||
+ | |freq_avx512_3=2,600MHz | ||
+ | |freq_avx512_4=2,600MHz | ||
+ | |freq_avx512_5=2,000MHz | ||
+ | |freq_avx512_6=2,000MHz | ||
+ | |freq_avx512_7=2,000MHz | ||
+ | |freq_avx512_8=2,000MHz | ||
}} | }} |
Latest revision as of 18:00, 3 August 2022
Edit Values | |
Xeon Silver 4215R | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4215R |
Market | Server |
Introduction | February 24, 2020 (announced) February 24, 2020 (launched) |
Release Price | $794.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4200 |
Frequency | 3,200 MHz |
Turbo Frequency | 4,000 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake R |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 130 W |
Tcase | 0 °C – 79 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Silver 4215R is a 64-bit 8-core x86 mid-range performance server microprocessor introduced by Intel in early 2020. The Silver 4215R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 3.2 GHz with a TDP of 130 W and features a turbo boost frequency of up to 4.0 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 3,200MHz | 4,000MHz | 4,000MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz |
AVX2 | 2,000MHz | 3,600MHz | 3,600MHz | 3,300MHz | 3,300MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz |
AVX512 | 1,500MHz | 3,300MHz | 3,300MHz | 2,600MHz | 2,600MHz | 2,000MHz | 2,000MHz | 2,000MHz | 2,000MHz |
Facts about "Xeon Silver 4215R - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4215R - Intel#pcie + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 32 + |
core count | 8 + |
core family | 6 + |
core name | Cascade Lake R + |
designer | Intel + |
family | Xeon Silver + |
first announced | February 24, 2020 + |
first launched | February 24, 2020 + |
full page name | intel/xeon silver/4215r + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | February 24, 2020 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 352.15 K (79 °C, 174.2 °F, 633.87 °R) + |
max cpu count | 2 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 4215R + |
name | Xeon Silver 4215R + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 794.00 (€ 714.60, £ 643.14, ¥ 82,044.02) + |
release price (tray) | $ 794.00 (€ 714.60, £ 643.14, ¥ 82,044.02) + |
series | 4200 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 9.6 GT/s + |
smp max ways | 2 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 130 W (130,000 mW, 0.174 hp, 0.13 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |