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Difference between revisions of "intel/xeon gold/6258r"
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|tcase max=74 °C
 
|tcase max=74 °C
 
|package name 1=intel,fclga_3647
 
|package name 1=intel,fclga_3647
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}}
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'''Xeon Gold 6258R''' is a {{arch|64}} [[28-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 6258R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
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 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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{{cache size
 +
|l1 cache=1.75 MiB
 +
|l1i cache=896 KiB
 +
|l1i break=28x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=896 KiB
 +
|l1d break=28x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=28 MiB
 +
|l2 break=28x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=38.5 MiB
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|l3 break=28x1.375 MiB
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|l3 desc=11-way set associative
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|l3 policy=write-back
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}}
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 +
== Memory controller ==
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{{memory controller
 +
|type=DDR4-2933
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|ecc=Yes
 +
|max mem=1 TiB
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|controllers=2
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|channels=6
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|max bandwidth=131.13 GiB/s
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|bandwidth schan=21.86 GiB/s
 +
|bandwidth dchan=43.71 GiB/s
 +
|bandwidth qchan=87.42 GiB/s
 +
|bandwidth hchan=131.13 GiB/s
 +
}}
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 +
== Expansions ==
 +
{{expansions main
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|
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=1x16
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|pcie config 2=x8
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|pcie config 3=x4
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}}
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}}
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 +
== Features ==
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{{x86 features
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|real=Yes
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|protected=Yes
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|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|sse_gfni=No
 +
|avx=Yes
 +
|avx_gfni=No
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=2
 +
|avx512gfni=No
 +
|avx512vaes=No
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|avx512vbmi2=No
 +
|avx512bitalg=No
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|avx512vpclmulqdq=No
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|abm=Yes
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|tbm=No
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|bmi1=Yes
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|bmi2=Yes
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|fma3=Yes
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|fma4=No
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|aes=Yes
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|rdrand=Yes
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|sha=No
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|xop=No
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|adx=Yes
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|clmul=Yes
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|f16c=Yes
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|bfloat16=No
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|tbt1=No
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|tbt2=Yes
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|tbmt3=No
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|tvb=No
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|bpt=No
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|eist=Yes
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|sst=Yes
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|flex=No
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|fastmem=No
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|ivmd=Yes
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|intelnodecontroller=No
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|intelnode=Yes
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|kpt=Yes
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|ptt=Yes
 +
|intelrunsure=No
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|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
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|osguard=No
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|intqat=No
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|dlboost=Yes
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|3dnow=No
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|e3dnow=No
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|smartmp=No
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|powernow=No
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|amdvi=No
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|amdv=No
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|amdsme=No
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|amdtsme=No
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|amdsev=No
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|rvi=No
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|smt=No
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|sensemi=No
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|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}

Latest revision as of 01:32, 28 February 2020

Edit Values
Xeon Gold 6258R
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6258R
MarketServer
IntroductionFebruary 24, 2020 (announced)
February 24, 2020 (launched)
Release Price$3,950.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency2,700 MHz
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier27
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake R
Core Family6
Core Model85
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores28
Threads56
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate10.4 GT/s
Electrical
TDP205 W
Tcase0 °C – 74 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 6258R is a 64-bit 28-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 6258R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports 2 AVX-512 FMA units as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.0 GHz.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associativewrite-back
L2$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB16-way set associativewrite-back
L3$38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
  28x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost
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