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{{nervana title|NNP-T 1300}}
 
{{nervana title|NNP-T 1300}}
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'''NNP-T 1300''' is a [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on TSMC [[16 nm process]] based on the {{nervana|Spring Crest|l=arch}} microarchitecture, the NNP-T 1300 has 22 {{nervana|Spring Crest#Tensor Processing Cluster (TPC)|TPCs|l=arch}} along with 55 MiB of scratchpad memory and operates at up to 950 MHz. This chip comes in a PCIe 4.0 [[accelerator card]] form factor and incorporates 32 GiB of [[HBM2]] memory. This NPU exposes 16 {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}} for scale-out capabilities.
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|name=NNP-T 1300
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|image=spring crest package (front).png
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|back image=spring crest package (back).png
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|caption=NPU with 4 HBM2 stacks
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|designer=Intel
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|manufacturer=TSMC
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|model number=NNP-T 1300
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|market=Server
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|first announced=November 12, 2019
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|first launched=November 12, 2019
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|family=NNP
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|series=NNP-T
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|frequency=950 MHz
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|microarch=Spring Crest
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|process=16 nm
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|transistors=27,000,000,000
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|technology=CMOS
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|die area=680 mm²
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|core count=22
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|max memory=32 GiB
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|smp interconnect=InterChip Link
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|smp interconnect links=16
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|smp interconnect rate=28 GT/s
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|power=150 W
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|tdp=300 W
 +
|package name 1=intel,fcbga_3325
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}}
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'''NNP-T 1300''' is a [[training]] [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on TSMC [[16 nm process]] based on the {{nervana|Spring Crest|l=arch}} microarchitecture, the NNP-T 1300 has 22 {{nervana|Spring Crest#Tensor Processing Cluster (TPC)|TPCs|l=arch}} along with 55 MiB of scratchpad memory and operates at up to 950 MHz. This chip comes in a PCIe 4.0 [[accelerator card]] form factor and incorporates 32 GiB of [[HBM2]] memory. This NPU exposes 16 {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}} for scale-out capabilities.
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== Peak Performance ==
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The NNP-T 1300 has a peak performance of [[peak flops (half-precision)::93.39 TFLOPS]] ([[bfloat16]]).
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== Cache ==
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{{main|nervana/microarchitectures/spring_crest#Memory_Hierarchy|l1=Spring Crest § Cache}}
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* 55 MiB of tightly-coupled scratchpad memory
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** 22 x 2.5 MiB/core
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== Memory controller ==
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{{memory controller
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|type=HBM2-2400
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|ecc=Yes
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|max mem=32 GiB
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|controllers=4
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|channels=32
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|max bandwidth=1.2288 TB/s
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}}
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== Interconnect Topology ==
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The NNP-T 1300 comes in a dual-slot standard PCIe 4.0 card which enables support for only the ring topology. Chips are interconnected using the 16 available {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}}.
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== Die ==
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{{main|nervana/microarchitectures/spring_crest#Die|l1=Spring Crest § Die}}
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* 27,000,000,000 transistors
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* 680 mm² die size
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:[[File:spring crest floorplan.png|400px|link=nervana/microarchitectures/spring_crest#Die]]
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== Product Brief ==
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* [[:File:16433-1 NNP-announce NNP-T brief v4.3.pdf|Intel NNP-T Product Brief]]

Latest revision as of 09:51, 1 February 2020

Edit Values
NNP-T 1300
spring crest package (front).png
NPU with 4 HBM2 stacks
General Info
DesignerIntel
ManufacturerTSMC
Model NumberNNP-T 1300
MarketServer
IntroductionNovember 12, 2019 (announced)
November 12, 2019 (launched)
ShopAmazon
General Specs
FamilyNNP
SeriesNNP-T
Frequency950 MHz
Microarchitecture
MicroarchitectureSpring Crest
Process16 nm
Transistors27,000,000,000
TechnologyCMOS
Die680 mm²
Cores22
Max Memory32 GiB
Multiprocessing
InterconnectInterChip Link
Interconnect Links16
Interconnect Rate28 GT/s
Electrical
Power dissipation150 W
TDP300 W
Packaging
PackageFCBGA-3325 (FCBGA)
Dimension60 mm × 60 mm
Contacts3325
spring crest package (back).png

NNP-T 1300 is a training neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on TSMC 16 nm process based on the Spring Crest microarchitecture, the NNP-T 1300 has 22 TPCs along with 55 MiB of scratchpad memory and operates at up to 950 MHz. This chip comes in a PCIe 4.0 accelerator card form factor and incorporates 32 GiB of HBM2 memory. This NPU exposes 16 inter-chip links for scale-out capabilities.

Peak Performance[edit]

The NNP-T 1300 has a peak performance of 93.39 TFLOPS
93,390,000,000,000 FLOPS
93,390,000,000 KFLOPS
93,390,000 MFLOPS
93,390 GFLOPS
0.0934 PFLOPS
(bfloat16).

Cache[edit]

Main article: Spring Crest § Cache
  • 55 MiB of tightly-coupled scratchpad memory
    • 22 x 2.5 MiB/core

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeHBM2-2400
Supports ECCYes
Max Mem32 GiB
Controllers4
Channels32
Max Bandwidth1.2288 TB/s
1,144.409 GiB/s
1,171,875 MiB/s
1,228.8 GB/s
1,228,800 MB/s
1.118 TiB/s

Interconnect Topology[edit]

The NNP-T 1300 comes in a dual-slot standard PCIe 4.0 card which enables support for only the ring topology. Chips are interconnected using the 16 available inter-chip links.

Die[edit]

Main article: Spring Crest § Die
  • 27,000,000,000 transistors
  • 680 mm² die size


spring crest floorplan.png

Product Brief[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=nervana/nnp/nnp-t_1300&oldid=95711"
Facts about "NNP-T 1300 - Intel Nervana"
RDF feed
back imageFile:spring crest package (back).png +
base frequency950 MHz (0.95 GHz, 950,000 kHz) +
core count22 +
designerIntel +
die area680 mm² (1.054 in², 6.8 cm², 680,000,000 µm²) +
familyNNP +
first announcedNovember 12, 2019 +
first launchedNovember 12, 2019 +
full page namenervana/nnp/nnp-t 1300 +
has ecc memory supporttrue +
instance ofmicroprocessor +
ldateNovember 12, 2019 +
main imageFile:spring crest package (front).png +
main image captionNPU with 4 HBM2 stacks +
manufacturerTSMC +
market segmentServer +
max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth1,144.409 GiB/s (1,171,875 MiB/s, 1,228.8 GB/s, 1,228,800 MB/s, 1.118 TiB/s, 1.229 TB/s) +
max memory channels32 +
microarchitectureSpring Crest +
model numberNNP-T 1300 +
nameNNP-T 1300 +
packageFCBGA-3325 +
peak flops (half-precision)93,390,000,000,000 FLOPS (93,390,000,000 KFLOPS, 93,390,000 MFLOPS, 93,390 GFLOPS, 93.39 TFLOPS, 0.0934 PFLOPS, 9.339e-5 EFLOPS, 9.339e-8 ZFLOPS) +
power dissipation150 W (150,000 mW, 0.201 hp, 0.15 kW) +
process16 nm (0.016 μm, 1.6e-5 mm) +
seriesNNP-T +
smp interconnectInterChip Link +
smp interconnect links16 +
smp interconnect rate28 GT/s +
supported memory typeHBM2-2400 +
tdp300 W (300,000 mW, 0.402 hp, 0.3 kW) +
technologyCMOS +
transistor count27,000,000,000 +