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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Mongoose 5
+
|name=Exynos M5 (Lion)
 
|designer=Samsung
 
|designer=Samsung
 
|manufacturer=Samsung
 
|manufacturer=Samsung
 
|introduction=2020
 
|introduction=2020
−
|process=8 nm
+
|process=7 nm
−
|predecessor=M4
+
|cores=2
 +
|type=Superscalar
 +
|type 2=Superpipeline
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages=16
 +
|decode=6-way
 +
|isa=ARMv8.2
 +
|l1i=64 KiB
 +
|l1i per=core
 +
|l1i desc=4-way set associative
 +
|l1d=64 KiB
 +
|l1d per=core
 +
|l1d desc=8-way set associative
 +
|l2=512 KiB
 +
|l2 per=core
 +
|l2 desc=8-way set associative
 +
|l3=2 MiB
 +
|l3 per=cluster
 +
|l3 desc=16-way set associative
 +
|predecessor=M4 (Cheetah)
 
|predecessor link=samsung/microarchitectures/m4
 
|predecessor link=samsung/microarchitectures/m4
−
|successor=M6
 
−
|successor link=samsung/microarchitectures/m6
 
 
}}
 
}}
−
'''Exynos Mongoose 5''' ('''M5''') is the successor to the {{\\|Mongoose 4}}, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics. According to [[Ice Universe]], it would be cancelled.<ref>https://www.androidcentral.com/new-report-says-samsung-ditching-custom-cpu-cores-arm-designs
+
'''Exynos M5''' ('''Lion''') <aka ''{{\\|Mongoose 5}}'' > is the successor to the [[Exynos]] {{\\|M4}} (Cheetah) <aka ''{{\\|Mongoose 4}}'' >, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
−
</ref>
 
−
 
 
−
 
 
−
{{future information}}
 
  
 
== Process Technology ==
 
== Process Technology ==
−
The M5 is planned to be fabricated on Samsung's [[7 nm process]] (7LPP).
+
The M5 is fabricated on Samsung's [[7 nm process]] (7LPP).
  
 
== Compiler support ==
 
== Compiler support ==
Line 33: Line 48:
 
== Architecture ==
 
== Architecture ==
  
−
=== Key changes from {{\\|M4}} ===
+
=== Key changes from {{\\|M4}} (Cheetah) ===
−
{{empty section}}
+
* Front end
 +
** Larger [[instruction queue]] (60 entries, up from 48)
 +
** Improved mispredict penalty (15 cycles, down from 16)
 +
* Back end
 +
** LSU execution units reorganized
 +
*** Two new 32b integer ALU pipes
 +
** Floating-point execution units reorganized
 +
*** Three new dedicted {{arm|NEON}} [[dot product]] EUs
 +
{{expand list}}
 +
 
 +
=== Block Diagram ===
 +
==== Individual Core ====
 +
 
 +
[[File:mongoose 5 block diagram.svg|950px]]
 +
 
 +
=== Memory Hierarchy ===
 +
{| border="0" cellpadding="5" width="100%"
 +
|-
 +
|width="50%" valign="top" align="left"|
 +
* Cache
 +
** L1I Caches
 +
*** 64 KiB, 4-way set associative
 +
**** 128 B line size, per core
 +
*** Parity-protected
 +
** L1D Cache
 +
*** 64 KiB, 8-way set associative
 +
**** 64 B line size, per core
 +
*** 4 cycles for fastest load-to-use
 +
*** 32 B/cycle load bandwidth
 +
*** 16 B/cycle store bandwidth
 +
** L2 Cache
 +
*** 512 KiB, 8-way set associative
 +
*** Inclusive of L1
 +
*** 12 cycles latency
 +
*** 32 B/cycle bandwidth
 +
** L3 Cache
 +
*** 2 MiB, 16-way set associative
 +
**** 1 MiB slice/core
 +
*** Exlusive of L2
 +
*** ~37-cycle typical (NUCA)
 +
** BIU
 +
*** 80 outstanding transactions
 +
|width="50%" valign="top" align="left"|
 +
The M3 TLB consists of dedicated L1 TLB for instruction <br>cache (ITLB) and another one for data cache (DTLB). <br>Additionally, there is a unified L2 TLB (STLB).
 +
 
 +
* TLBs
 +
** ITLB
 +
*** 512-entry
 +
** DTLB
 +
*** 32-entry
 +
*** 512-entry Mid-level DTLB
 +
** STLB
 +
*** 4,096-entry, per core
 +
 
 +
* BPU
 +
** 4K-entry main BTB
 +
** 128-entry µBTB
 +
** 64-entry return stack
 +
** 16K-entry L2 BTB
 +
|}
 +
 
 +
== All M5 Processors ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc5 tc6 tc7">
 +
{{comp table header|main|7:List of M5-based Processors}}
 +
{{comp table header|main|5:Main processor|2:Integrated Graphics}}
 +
{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency}}
 +
{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::~*M5*||Mongoose 5||Exynos 5]]
 +
|?full page name
 +
|?model number
 +
|?family
 +
|?first launched
 +
|?microarchitecture
 +
|?core count
 +
|?base frequency#GHz
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|format=template
 +
|template=proc table 3
 +
|userparam=9
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::~*M5*||Mongoose 5||Exynos 5]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
== Bibliography ==
 +
* LLVM: lib/Target/AArch64/AArch64SchedExynosM5.td

Latest revision as of 12:56, 22 January 2026

Edit Values
Exynos M5 (Lion) µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
Introduction2020
Process7 nm
Core Configs2
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages16
Decode6-way
Instructions
ISAARMv8.2
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache64 KiB/core
8-way set associative
L2 Cache512 KiB/core
8-way set associative
L3 Cache2 MiB/cluster
16-way set associative
Succession

Exynos M5 (Lion) <aka Mongoose 5 > is the successor to the Exynos M4 (Cheetah) <aka Mongoose 4 >, a 7 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology[edit]

The M5 is fabricated on Samsung's 7 nm process (7LPP).

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
GCC -mcpu=exynos-m5 -mtune=exynos-m5
LLVM -mcpu=exynos-m5 -mtune=exynos-m5

Architecture[edit]

Key changes from M4 (Cheetah)[edit]

  • Front end
    • Larger instruction queue (60 entries, up from 48)
    • Improved mispredict penalty (15 cycles, down from 16)
  • Back end
    • LSU execution units reorganized
      • Two new 32b integer ALU pipes
    • Floating-point execution units reorganized

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Individual Core[edit]

mongoose 5 block diagram.svg

Memory Hierarchy[edit]

  • Cache
    • L1I Caches
      • 64 KiB, 4-way set associative
        • 128 B line size, per core
      • Parity-protected
    • L1D Cache
      • 64 KiB, 8-way set associative
        • 64 B line size, per core
      • 4 cycles for fastest load-to-use
      • 32 B/cycle load bandwidth
      • 16 B/cycle store bandwidth
    • L2 Cache
      • 512 KiB, 8-way set associative
      • Inclusive of L1
      • 12 cycles latency
      • 32 B/cycle bandwidth
    • L3 Cache
      • 2 MiB, 16-way set associative
        • 1 MiB slice/core
      • Exlusive of L2
      • ~37-cycle typical (NUCA)
    • BIU
      • 80 outstanding transactions

The M3 TLB consists of dedicated L1 TLB for instruction
cache (ITLB) and another one for data cache (DTLB).
Additionally, there is a unified L2 TLB (STLB).

  • TLBs
    • ITLB
      • 512-entry
    • DTLB
      • 32-entry
      • 512-entry Mid-level DTLB
    • STLB
      • 4,096-entry, per core
  • BPU
    • 4K-entry main BTB
    • 128-entry µBTB
    • 64-entry return stack
    • 16K-entry L2 BTB

All M5 Processors[edit]

 List of M5-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedArchCoresFrequencyGPUFrequency
990Exynos2020Mongoose 5, Cortex-A76, Cortex-A5582.6 GHz
2,600 MHz
2,600,000 kHz
, 3 GHz
3,000 MHz
3,000,000 kHz
, 2.1 GHz
2,100 MHz
2,100,000 kHz
Mali-G77832 MHz
0.832 GHz
832,000 KHz
Count: 1

Bibliography[edit]

  • LLVM: lib/Target/AArch64/AArch64SchedExynosM5.td
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/microarchitectures/m5&oldid=104120"
Facts about "Exynos M5 - Microarchitectures - Samsung"
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codenameExynos M5 (Lion) +
core count2 +
designerSamsung +
first launched2020 +
full page namesamsung/microarchitectures/m5 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerSamsung +
microarchitecture typeCPU +
nameExynos M5 (Lion) +
pipeline stages16 +
process7 nm (0.007 μm, 7.0e-6 mm) +