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{{core | {{core | ||
|name=Cascade Lake W | |name=Cascade Lake W | ||
− | | | + | |image=cascade-lake-w (front).png |
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |first announced=2019 | + | |first announced=October 7, 2019 |
− | |first launched=2019 | + | |first launched=October 7, 2019 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 13: | Line 13: | ||
|word=64 bit | |word=64 bit | ||
|proc=14 nm | |proc=14 nm | ||
+ | |package name 1=intel,fclga_2066 | ||
|predecessor=Skylake W | |predecessor=Skylake W | ||
|predecessor link=intel/cores/skylake_w | |predecessor link=intel/cores/skylake_w | ||
}} | }} | ||
− | '''Cascade Lake W''' ('''Cascade Lake Workstations'''; '''CLS-W''') is codename for [[Intel]]'s enterprise workstation microprocessor line based on the {{intel|Cascade Lake|l=arch}} microarchitecture, succeeding {{\\|Skylake W}}. Cascade Lake W processors feature a {{intel|Cascade Lake#Key changes from Skylake|number of enhancements|l=arch}} including a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads | + | '''Cascade Lake W''' ('''Cascade Lake Workstations'''; '''CLS-W''') is codename for [[Intel]]'s enterprise workstation microprocessor line based on the {{intel|Cascade Lake|l=arch}} microarchitecture, succeeding {{\\|Skylake W}}. Cascade Lake W processors feature a {{intel|Cascade Lake#Key changes from Skylake|number of enhancements|l=arch}} including a new {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads. Cascade Lake W series of processors are branded as the {{intel|Xeon W}} family. |
== Overview == | == Overview == | ||
− | Cascade | + | Cascade Lake W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the {{intel|Lewisburg|l=chipset}} chipset. All processors are socket {{intel|FCLGA-3647}}, manufactured on Intel's [[14 nm process|enhanced 14++ nm process]] based on the {{intel|Cascade Lake|Skylake|l=arch}} microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as {{intel|vPro}}, {{intel|Volume Management Device}} (VMD), and RAS. |
=== Common Features === | === Common Features === | ||
For the most part, Cascade Lake W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that the Skylake W come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models (with the exception of the two low-end models). All models have 48 [[PCIe]] lanes and have all the following features in common: | For the most part, Cascade Lake W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature. It's worth pointing out that the Skylake W come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models (with the exception of the two low-end models). All models have 48 [[PCIe]] lanes and have all the following features in common: | ||
− | * '''Mem:''' | + | * '''Mem:''' 1 TiB of quad-channel DDR4-2933 ECC Memory |
+ | ** ''M'' models support 2 TiB of memory | ||
** DPC RDIMM and LRDIMM \w [[ECC]] | ** DPC RDIMM and LRDIMM \w [[ECC]] | ||
− | * '''I/O:''' | + | * '''I/O:''' 64 [[PCIe]] 3.0 Lanes |
* '''TDP:''' 160 W - 205 W | * '''TDP:''' 160 W - 205 W | ||
− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}}) | + | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}} with 2 FMA units) |
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD). | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD). | ||
− | |||
== Cascade Lake W Processors == | == Cascade Lake W Processors == | ||
Note that for the lower [[core-count]] models, the [[L3 cache]] size is larger than it would otherwise be due to additional cache slices being enabled from disabled [[physical core|cores]]. | Note that for the lower [[core-count]] models, the [[L3 cache]] size is larger than it would otherwise be due to additional cache slices being enabled from disabled [[physical core|cores]]. | ||
− | |||
− | |||
<!-- NOTE: | <!-- NOTE: | ||
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<table class="comptable sortable tc4 tc5 tc11"> | <table class="comptable sortable tc4 tc5 tc11"> | ||
{{comp table header|main|10:List of Cascade Lake W-based Processors}} | {{comp table header|main|10:List of Cascade Lake W-based Processors}} | ||
− | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo| | + | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%{{intel|turbo boost|Turbo}}|%{{intel|turbo boost max|Turbo Max}}}} |
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake W]] | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake W]] | ||
|?full page name | |?full page name | ||
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|?base frequency#GHz | |?base frequency#GHz | ||
|?turbo frequency (1 core)#GHz | |?turbo frequency (1 core)#GHz | ||
− | |? | + | |?intel turbo boost max technology 3 0 frequency#GHz |
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 |
Latest revision as of 11:34, 7 October 2019
Edit Values | |
Cascade Lake W | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Introduction | October 7, 2019 (announced) October 7, 2019 (launched) |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Glacier Falls |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Packaging | |
Package | FCLGA-2066 (LGA) |
Dimension | 52.5 mm × 45 mm |
Pitch | 1.016 mm |
Contacts | 2066 |
Socket | Socket R4 |
Succession | |
Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads. Cascade Lake W series of processors are branded as the Xeon W family.
Overview[edit]
Cascade Lake W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the Lewisburg chipset. All processors are socket FCLGA-3647, manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.
Common Features[edit]
For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:
- Mem: 1 TiB of quad-channel DDR4-2933 ECC Memory
- M models support 2 TiB of memory
- DPC RDIMM and LRDIMM \w ECC
- I/O: 64 PCIe 3.0 Lanes
- TDP: 160 W - 205 W
- ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX-512-F/CD/BW/DQ/VL/VNNI with 2 FMA units)
- Features: Speed Shift, vPro, VT-x/EPT, VT-d, TBT 2.0, TSX, TXT, SpeedStep, Identity Protection, Secure Key, MPX, OS Guard, and Volume Management Device (VMD).
Cascade Lake W Processors[edit]
Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.
See also[edit]
|
designer | Intel + |
first announced | October 7, 2019 + |
first launched | October 7, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | ![]() |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake W + |
package | FCLGA-2066 + |
platform | Glacier Falls + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R4 + |
word size | 64 bit (8 octets, 16 nibbles) + |