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Difference between revisions of "intel/xeon gold/6252"
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{{intel title|Xeon Gold 6252}} | {{intel title|Xeon Gold 6252}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Xeon Gold 6252 | ||
+ | |image=cascade lake sp (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=6252 | ||
+ | |part number=CD8069504194401 | ||
+ | |part number 2=BX806956252 | ||
+ | |s-spec=SRF91 | ||
+ | |s-spec qs=QRAL | ||
+ | |market=Server | ||
+ | |first announced=April 2, 2019 | ||
+ | |first launched=April 2, 2019 | ||
+ | |release price (tray)=$3,655.00 | ||
+ | |release price (box)=$3,662.00 | ||
+ | |family=Xeon Gold | ||
+ | |series=6200 | ||
+ | |locked=Yes | ||
+ | |frequency=2,100 MHz | ||
+ | |turbo frequency1=3,700 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=21 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Cascade Lake | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Cascade Lake SP | ||
+ | |core family=6 | ||
+ | |core model=85 | ||
+ | |core stepping=B0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=24 | ||
+ | |thread count=48 | ||
+ | |max memory=1 TiB | ||
+ | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=150 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=86 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |predecessor=Xeon Gold 6152 | ||
+ | |predecessor link=intel/xeon_gold/6152 | ||
+ | }} | ||
'''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6252 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. | '''Xeon Gold 6252''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6252 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. | ||
Line 6: | Line 55: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
− | The Xeon | + | The Xeon Gold 6252 features a larger non-default 35.75 MiB of [[L3]], a size that would normally be found on a 26-core part. |
{{cache size | {{cache size | ||
|l1 cache=1.5 MiB | |l1 cache=1.5 MiB | ||
Line 24: | Line 73: | ||
|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2933 | ||
+ | |ecc=Yes | ||
+ | |max mem=1 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=131.13 GiB/s | ||
+ | |bandwidth schan=21.86 GiB/s | ||
+ | |bandwidth dchan=43.71 GiB/s | ||
+ | |bandwidth qchan=87.42 GiB/s | ||
+ | |bandwidth hchan=131.13 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=48 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,100MHz | ||
+ | |freq_1=3,700MHz | ||
+ | |freq_2=3,700MHz | ||
+ | |freq_3=3,500MHz | ||
+ | |freq_4=3,500MHz | ||
+ | |freq_5=3,400MHz | ||
+ | |freq_6=3,400MHz | ||
+ | |freq_7=3,400MHz | ||
+ | |freq_8=3,400MHz | ||
+ | |freq_9=3,400MHz | ||
+ | |freq_10=3,400MHz | ||
+ | |freq_11=3,400MHz | ||
+ | |freq_12=3,400MHz | ||
+ | |freq_13=3,200MHz | ||
+ | |freq_14=3,200MHz | ||
+ | |freq_15=3,200MHz | ||
+ | |freq_16=3,200MHz | ||
+ | |freq_17=3,000MHz | ||
+ | |freq_18=3,000MHz | ||
+ | |freq_19=3,000MHz | ||
+ | |freq_20=3,000MHz | ||
+ | |freq_21=2,800MHz | ||
+ | |freq_22=2,800MHz | ||
+ | |freq_23=2,800MHz | ||
+ | |freq_24=2,800MHz | ||
+ | |freq_avx2_base=1,700MHz | ||
+ | |freq_avx2_1=3,600MHz | ||
+ | |freq_avx2_2=3,600MHz | ||
+ | |freq_avx2_3=3,400MHz | ||
+ | |freq_avx2_4=3,400MHz | ||
+ | |freq_avx2_5=3,300MHz | ||
+ | |freq_avx2_6=3,300MHz | ||
+ | |freq_avx2_7=3,300MHz | ||
+ | |freq_avx2_8=3,300MHz | ||
+ | |freq_avx2_9=3,100MHz | ||
+ | |freq_avx2_10=3,100MHz | ||
+ | |freq_avx2_11=3,100MHz | ||
+ | |freq_avx2_12=3,100MHz | ||
+ | |freq_avx2_13=2,800MHz | ||
+ | |freq_avx2_14=2,800MHz | ||
+ | |freq_avx2_15=2,800MHz | ||
+ | |freq_avx2_16=2,800MHz | ||
+ | |freq_avx2_17=2,500MHz | ||
+ | |freq_avx2_18=2,500MHz | ||
+ | |freq_avx2_19=2,500MHz | ||
+ | |freq_avx2_20=2,500MHz | ||
+ | |freq_avx2_21=2,400MHz | ||
+ | |freq_avx2_22=2,400MHz | ||
+ | |freq_avx2_23=2,400MHz | ||
+ | |freq_avx2_24=2,400MHz | ||
+ | |freq_avx512_base=1,300MHz | ||
+ | |freq_avx512_1=3,500MHz | ||
+ | |freq_avx512_2=3,500MHz | ||
+ | |freq_avx512_3=3,300MHz | ||
+ | |freq_avx512_4=3,300MHz | ||
+ | |freq_avx512_5=3,000MHz | ||
+ | |freq_avx512_6=3,000MHz | ||
+ | |freq_avx512_7=3,000MHz | ||
+ | |freq_avx512_8=3,000MHz | ||
+ | |freq_avx512_9=2,600MHz | ||
+ | |freq_avx512_10=2,600MHz | ||
+ | |freq_avx512_11=2,600MHz | ||
+ | |freq_avx512_12=2,600MHz | ||
+ | |freq_avx512_13=2,300MHz | ||
+ | |freq_avx512_14=2,300MHz | ||
+ | |freq_avx512_15=2,300MHz | ||
+ | |freq_avx512_16=2,300MHz | ||
+ | |freq_avx512_17=2,100MHz | ||
+ | |freq_avx512_18=2,100MHz | ||
+ | |freq_avx512_19=2,100MHz | ||
+ | |freq_avx512_20=2,100MHz | ||
+ | |freq_avx512_21=2,000MHz | ||
+ | |freq_avx512_22=2,000MHz | ||
+ | |freq_avx512_23=2,000MHz | ||
+ | |freq_avx512_24=2,000MHz | ||
}} | }} |
Latest revision as of 02:18, 29 December 2019
Edit Values | |
Xeon Gold 6252 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6252 |
Part Number | CD8069504194401, BX806956252 |
S-Spec | SRF91 QRAL (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $3,655.00 (tray) $3,662.00 (box) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 21 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 86 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6252 is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6252 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.7 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
The Xeon Gold 6252 features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | ||
Normal | 2,100MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,200MHz | 3,200MHz | 3,200MHz | 3,200MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz |
AVX2 | 1,700MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,100MHz | 3,100MHz | 3,100MHz | 3,100MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz |
AVX512 | 1,300MHz | 3,500MHz | 3,500MHz | 3,300MHz | 3,300MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,300MHz | 2,300MHz | 2,300MHz | 2,300MHz | 2,100MHz | 2,100MHz | 2,100MHz | 2,100MHz | 2,000MHz | 2,000MHz | 2,000MHz | 2,000MHz |
Facts about "Xeon Gold 6252 - Intel"
full page name | intel/xeon gold/6252 + |
instance of | microprocessor + |
ldate | 1900 + |