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{{intel title|Xeon Gold 6248}}
 
{{intel title|Xeon Gold 6248}}
−
{{chip}}
+
{{chip
 +
|name=Xeon Gold 6248
 +
|image=cascade lake sp (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=6248
 +
|part number=CD8069504194301
 +
|part number 2=BX806956248
 +
|s-spec=SRF90
 +
|s-spec qs=QRAK
 +
|market=Server
 +
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|release price (tray)=$3,072.00
 +
|release price (box)=$3,078.00
 +
|family=Xeon Gold
 +
|series=6200
 +
|locked=Yes
 +
|frequency=2,500 MHz
 +
|turbo frequency1=3,900 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=25
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake SP
 +
|core family=6
 +
|core model=85
 +
|core stepping=B0
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=20
 +
|thread count=40
 +
|max memory=1 TiB
 +
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=150 W
 +
|tcase min=0 °C
 +
|tcase max=86 °C
 +
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Gold 6148
 +
|predecessor link=intel/xeon_gold/6148
 +
}}
 
'''Xeon Gold 6248''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6248 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
 
'''Xeon Gold 6248''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6248 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
 +
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 +
{{cache size
 +
|l1 cache=1.25 MiB
 +
|l1i cache=640 KiB
 +
|l1i break=20x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=640 KiB
 +
|l1d break=20x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=20 MiB
 +
|l2 break=20x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=27.5 MiB
 +
|l3 break=20x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2933
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=131.13 GiB/s
 +
|bandwidth schan=21.86 GiB/s
 +
|bandwidth dchan=43.71 GiB/s
 +
|bandwidth qchan=87.42 GiB/s
 +
|bandwidth hchan=131.13 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
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|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,500MHz
 +
|freq_1=3,900MHz
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|freq_2=3,900MHz
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|freq_3=3,700MHz
 +
|freq_4=3,700MHz
 +
|freq_5=3,600MHz
 +
|freq_6=3,600MHz
 +
|freq_7=3,600MHz
 +
|freq_8=3,600MHz
 +
|freq_9=3,600MHz
 +
|freq_10=3,600MHz
 +
|freq_11=3,600MHz
 +
|freq_12=3,600MHz
 +
|freq_13=3,400MHz
 +
|freq_14=3,400MHz
 +
|freq_15=3,400MHz
 +
|freq_16=3,400MHz
 +
|freq_17=3,200MHz
 +
|freq_18=3,200MHz
 +
|freq_19=3,200MHz
 +
|freq_20=3,200MHz
 +
|freq_avx2_base=1,900MHz
 +
|freq_avx2_1=3,800MHz
 +
|freq_avx2_2=3,800MHz
 +
|freq_avx2_3=3,600MHz
 +
|freq_avx2_4=3,600MHz
 +
|freq_avx2_5=3,500MHz
 +
|freq_avx2_6=3,500MHz
 +
|freq_avx2_7=3,500MHz
 +
|freq_avx2_8=3,500MHz
 +
|freq_avx2_9=3,400MHz
 +
|freq_avx2_10=3,400MHz
 +
|freq_avx2_11=3,400MHz
 +
|freq_avx2_12=3,400MHz
 +
|freq_avx2_13=3,000MHz
 +
|freq_avx2_14=3,000MHz
 +
|freq_avx2_15=3,000MHz
 +
|freq_avx2_16=3,000MHz
 +
|freq_avx2_17=2,800MHz
 +
|freq_avx2_18=2,800MHz
 +
|freq_avx2_19=2,800MHz
 +
|freq_avx2_20=2,800MHz
 +
|freq_avx512_base=1,600MHz
 +
|freq_avx512_1=3,800MHz
 +
|freq_avx512_2=3,800MHz
 +
|freq_avx512_3=3,600MHz
 +
|freq_avx512_4=3,600MHz
 +
|freq_avx512_5=3,500MHz
 +
|freq_avx512_6=3,500MHz
 +
|freq_avx512_7=3,500MHz
 +
|freq_avx512_8=3,500MHz
 +
|freq_avx512_9=3,000MHz
 +
|freq_avx512_10=3,000MHz
 +
|freq_avx512_11=3,000MHz
 +
|freq_avx512_12=3,000MHz
 +
|freq_avx512_13=2,700MHz
 +
|freq_avx512_14=2,700MHz
 +
|freq_avx512_15=2,700MHz
 +
|freq_avx512_16=2,700MHz
 +
|freq_avx512_17=2,500MHz
 +
|freq_avx512_18=2,500MHz
 +
|freq_avx512_19=2,500MHz
 +
|freq_avx512_20=2,500MHz
 +
}}

Latest revision as of 01:17, 29 December 2019

Edit Values
Xeon Gold 6248
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6248
Part NumberCD8069504194301,
BX806956248
S-SpecSRF90
QRAK (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$3,072.00 (tray)
$3,078.00 (box)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency2,500 MHz
Turbo Frequency3,900 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier25
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Core SteppingB0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores20
Threads40
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP150 W
Tcase0 °C – 86 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6248 is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6248 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.5 GHz with a TDP of 150 W and features a turbo boost frequency of up to 3.9 GHz.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L1D$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associativewrite-back
L2$20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
  20x1 MiB16-way set associativewrite-back
L3$27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
  20x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
1234567891011121314151617181920
Normal2,500MHz3,900MHz3,900MHz3,700MHz3,700MHz3,600MHz3,600MHz3,600MHz3,600MHz3,600MHz3,600MHz3,600MHz3,600MHz3,400MHz3,400MHz3,400MHz3,400MHz3,200MHz3,200MHz3,200MHz3,200MHz
AVX21,900MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz3,400MHz3,400MHz3,400MHz3,400MHz3,000MHz3,000MHz3,000MHz3,000MHz2,800MHz2,800MHz2,800MHz2,800MHz
AVX5121,600MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz3,000MHz3,000MHz3,000MHz3,000MHz2,700MHz2,700MHz2,700MHz2,700MHz2,500MHz2,500MHz2,500MHz2,500MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6248&oldid=95169"
Facts about "Xeon Gold 6248 - Intel"
RDF feed
full page nameintel/xeon gold/6248 +
instance ofmicroprocessor +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description16-way set associative +
l2$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description11-way set associative +
l3$ size27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate1900 +