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{{hisilicon title|Kunpeng 920 (Hi1620)}}
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{{hisilicon title|Kunpeng 920-6426}}
 
{{chip
 
{{chip
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|future=Yes
+
|name=Kunpeng 920-6426
−
|name=Kunpeng 920
+
|image=kunpeng 920 (front).png
−
|no image=Yes
 
 
|designer=HiSilicon
 
|designer=HiSilicon
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|designer 2=ARM Holdings
+
|designer 2= <!--ARM Holdings-->
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|model number=Hi1620
+
|model number=920-6426
−
|part number=Hi1620
 
 
|market=Server
 
|market=Server
 
|first announced=September, 2018
 
|first announced=September, 2018
 
|first launched=January 7, 2019
 
|first launched=January 7, 2019
 
|family=Hi16xx
 
|family=Hi16xx
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|series=Kunpeng 920
+
|series=920
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|frequency=2,400 MHz
+
|frequency=2.6 GHz
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|frequency 2=2,600 MHz
+
|isa=ARMv8.2
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|frequency 3=3,000 MHz
 
−
|isa=ARMv8
 
 
|isa family=ARM
 
|isa family=ARM
−
|microarch=Custom
+
|microarch=TaiShan v110
 +
|core name=TaiShan v110
 +
|transistors=20,000,000,000
 
|technology=CMOS
 
|technology=CMOS
 +
|mcp=Yes
 +
|die count=3
 
|word size=64 bit
 
|word size=64 bit
 
|core count=64
 
|core count=64
 
|thread count=64
 
|thread count=64
 +
|max memory=2 TiB
 
|max cpus=4
 
|max cpus=4
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|max memory=512 GiB
+
|tdp=195 W
 
}}
 
}}
−
[[File:hi1620 exhibit sign.jpg|thumb|right|Hi1620 on exhibit.]]
 
−
'''Kunpeng 920''' ('''Hi1620''') is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by [[HiSilicon]] in late-2018. Fabricated by [[TSMC]] on a [[7 nm process]], this chip incorporates 64 custom cores operating at 2.4-3 GHz with a TDP of up to 200 W. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.
 
  
 +
'''Kunpeng 920-6426''' is a [[tetrahexaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by [[HiSilicon]] in early 2019. Fabricated by [[TSMC]] on a [[7 nm process|7nm HPC process]] based on the {{hisilicon|TaiSHan v110|l=arch}} microarchitecture, this chip incorporates 64 cores operating at 2.6 GHz with a TDP of 180 W. This chip supports up to 2 TiB of octa-channel DDR4-2933 memory.
  
−
{{unknown features}}
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[[File:hi1620 exhibit sign.jpg|thumb|left|Hi1620 on exhibit.]]
  
−
 
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== Cache ==
 
−
{{main|arm holdings/microarchitectures/ares#Memory_Hierarchy|l1=Ares § Cache}}
 
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{{cache size
 
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|l1 cache=8 MiB
 
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|l1i cache=4 MiB
 
−
|l1i break=64x64 KiB
 
−
|l1d cache=4 MiB
 
−
|l1d break=64x64 KiB
 
−
|l2 cache=32 MiB
 
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|l2 break=64x512 KiB
 
−
|l3 cache=64 MiB
 
−
|l3 break=64x1 MiB
 
−
}}
 
−
 
−
== Memory controller ==
 
−
{{memory controller
 
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|type=DDR4-3200
 
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|ecc=Yes
 
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|max mem=1 TiB
 
−
|controllers=1
 
−
|channels=8
 
−
|width=64 bit
 
−
|max bandwidth=190.7 GiB/s
 
−
|bandwidth schan=23.84 GiB/s
 
−
|bandwidth dchan=47.68 GiB/s
 
−
|bandwidth qchan=95.37 GiB/s
 
−
|bandwidth ochan=190.7 GiB/s
 
−
}}
 
  
 
== Expansions ==
 
== Expansions ==
Line 85: Line 56:
 
}}
 
}}
 
}}
 
}}
 +
 
== Features ==
 
== Features ==
 
{{arm features
 
{{arm features
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|pmuv3=No
 
|pmuv3=No
 
|crc32=Yes
 
|crc32=Yes
−
|crypto=No
+
|crypto=Yes
 
|fp=No
 
|fp=No
−
|fp16=No
+
|fp16=Yes
 
|profile=No
 
|profile=No
−
|ras=No
+
|ras=Yes
 
|simd=No
 
|simd=No
 
|rdm=No
 
|rdm=No
 +
}}
 +
 +
== Cache ==
 +
{{main|hisilicon/microarchitectures/taishan_v110#Memory_Hierarchy|l1=TaiShan v110 § Cache}}
 +
{{cache size
 +
|l1 cache=8 MiB
 +
|l1i cache=4 MiB
 +
|l1i break=64x64 KiB
 +
|l1d cache=4 MiB
 +
|l1d break=64x64 KiB
 +
|l2 cache=32 MiB
 +
|l2 break=64x512 KiB
 +
|l3 cache=64 MiB
 +
|l3 break=64x1 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2933
 +
|ecc=Yes
 +
|max mem=2 TiB
 +
|controllers=1
 +
|channels=8
 +
|width=64 bit
 +
|max bandwidth=190.7 GiB/s
 +
|bandwidth schan=23.84 GiB/s
 +
|bandwidth dchan=47.68 GiB/s
 +
|bandwidth qchan=95.37 GiB/s
 +
|bandwidth ochan=190.7 GiB/s
 
}}
 
}}
  
 
== Utilizing devices ==
 
== Utilizing devices ==
 
* [[used by::HiSilicon D06]]
 
* [[used by::HiSilicon D06]]
 +
* [[used by::TaiShan 2280]]
 
* [[used by::TaiShan 5280]]
 
* [[used by::TaiShan 5280]]
 
* [[used by::TaiShan 5290]]
 
* [[used by::TaiShan 5290]]
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{{expand list}}
 
{{expand list}}
−
 
−
== Bibliography ==
 
−
* Huawei. (January 7, 2018). [press release] "[https://www.huawei.com/en/press-events/news/2019/1/huawei-unveils-highest-performance-arm-based-cpu Huawei Unveils Industry's Highest-Performance ARM-based CPU Bringing Global Computing Power to Next Level]".
 

Latest revision as of 12:11, 24 March 2025

Edit Values
Kunpeng 920-6426
kunpeng 920 (front).png
General Info
DesignerHiSilicon
ManufacturerTSMC
Model Number920-6426
MarketServer
IntroductionSeptember, 2018 (announced)
January 7, 2019 (launched)
General Specs
FamilyHi16xx
Series920
Frequency2.6 GHz
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureTaiShan v110
Core NameTaiShan v110
Transistors20,000,000,000
TechnologyCMOS
MCPYes (3 dies)
Word Size64 bit
Cores64
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP195 W

Kunpeng 920-6426 is a tetrahexaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in early 2019. Fabricated by TSMC on a 7nm HPC process based on the TaiSHan v110 microarchitecture, this chip incorporates 64 cores operating at 2.6 GHz with a TDP of 180 W. This chip supports up to 2 TiB of octa-channel DDR4-2933 memory.

Hi1620 on exhibit.


Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 40
Configuration: x16, x8, x4
USBRevision: 3.0
Max Ports: 4
SATARevision: 3.0
Max Ports: 2


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FP16ARMv8.2-A half-precision floating-point extension
RASReliability, Availability, and Serviceability extension

Cache[edit]

Main article: TaiShan v110 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$8 MiB
8,192 KiB
8,388,608 B
L1I$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L1D$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  64x512 KiB  
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  64x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels8
Width64 bit
Max Bandwidth190.7 GiB/s
195,276.8 MiB/s
204.763 GB/s
204,762.566 MB/s
0.186 TiB/s
0.205 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Octa 190.7 GiB/s

Utilizing devices[edit]

  • HiSilicon D06
  • TaiShan 2280
  • TaiShan 5280
  • TaiShan 5290
  • TaiShan X6000

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/920-6426&oldid=103057"
Facts about "Kunpeng 920-6426 - HiSilicon"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Kunpeng 920-6426 - HiSilicon#pcie +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
core count64 +
core nameTaiShan v110 +
designerHiSilicon +
die count3 +
familyHi16xx +
first announcedSeptember 2018 +
first launchedJanuary 7, 2019 +
full page namehisilicon/kunpeng/920-6426 +
has ecc memory supporttrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isaARMv8.2 +
isa familyARM +
l1$ size8,192 KiB (8,388,608 B, 8 MiB) +
l1d$ size4,096 KiB (4,194,304 B, 4 MiB) +
l1i$ size4,096 KiB (4,194,304 B, 4 MiB) +
l2$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateJanuary 7, 2019 +
main imageFile:kunpeng 920 (front).png +
manufacturerTSMC +
market segmentServer +
max cpu count4 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
max sata ports2 +
max usb ports4 +
microarchitectureTaiShan v110 +
model number920-6426 +
nameKunpeng 920-6426 +
series920 +
smp max ways4 +
supported memory typeDDR4-2933 +
tdp195 W (195,000 mW, 0.261 hp, 0.195 kW) +
technologyCMOS +
thread count64 +
transistor count20,000,000,000 +
used byHiSilicon D06 +, TaiShan 2280 +, TaiShan 5280 +, TaiShan 5290 + and TaiShan X6000 +
word size64 bit (8 octets, 16 nibbles) +