Difference between revisions of "intel/xeon d/d-1623n"

	Edit Values
	Xeon D-1623N
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	D-1623N
Market	Server
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$256 (tray)
Shop	Amazon
	General Specs
Family	Xeon D
Series	D-1600
Locked	Yes
Frequency	2,400 MHz
Turbo Frequency	2,700 MHz (1 core)
Bus type	DMI 2.0
Clock multiplier	24
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Broadwell
Platform	Grangeville
Core Name	Hewitt Lake
Core Family	6
Core Model	6
Process	14 nm
Transistors	3,200,000,000
Technology	CMOS
Die	246.24 mm²
Word Size	64 bit
Cores	4
Threads	8
Max Memory	128 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	35 W
Tjunction	– 105 °C
Tcase	– 83 °C
	Packaging
Package	FCBGA-1667 (FCBGA)
Dimension	37.5 mm × 37.5 mm × 3.557 mm
Pitch	0.7 mm
Contacts	1667

Latest revision as of 06:42, 6 April 2019

Xeon D-1623N is a 64-bit quad-core x86 microserver SoC introduced by Intel in early 2019. The D-1623N is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.4 GHz with a TDP of 35 W and a turbo frequency of 2.7 GHz. This processor supports up to 128 GiB of dual-channel DDR4-1866 memory.

Cache[edit]

Main article: Broadwell § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	8-way set associative	write-back

L3$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

		4x1.5 MiB	16-way set associative	write-back

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-1866
Supports ECC	Yes
Max Mem	128 GiB
Controllers	1
Channels	2
Max Bandwidth	27.81 GiB/s 28,477.44 MiB/s 29.861 GB/s 29,860.76 MB/s 0.0272 TiB/s 0.0299 TB/s
Bandwidth	Single 13.9 GiB/s Double 27.81 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 24
	Configuration: x16, x8, x4

PCIe	Revision: 2.0
	Max Lanes: 8
	Configuration: x8, x4

USB	Revision: 3.0
	Max Ports: 4

USB	Revision: 2.0
	Max Ports: 4

SATA	Revision: 3
	Max Ports: 6

Networking[edit]

[Edit/Modify Network Info]

Networking

Ethernet

10GbE	Yes (Ports: 2)

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
QAT	Integrated QuickAssist Technology

@@ Line 35: / Line 35: @@
 |max memory=128 GiB
 |tdp=35 W
+|tjunc max=105 °C
+|tcase max=83 °C
 |package name 1=intel,fcbga_1667
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-1623N - Intel#pcie +
back image	+
base frequency	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
bus type	DMI 2.0 +
clock multiplier	24 +
core count	4 +
core family	6 +
core model	6 +
core name	Hewitt Lake +
designer	Intel +
die area	246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
family	Xeon D +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon d/d-1623n +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Secure Key Technology +, OS Guard + and Integrated QuickAssist Technology +
has integrated intel quickassist technology	true +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	356.15 K (83 °C, 181.4 °F, 641.07 °R) +
max cpu count	1 +
max memory	131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth	27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels	2 +
max sata ports	6 +
max storage temperature	378.15 K (105 °C, 221 °F, 680.67 °R) +
max usb ports	4 +
microarchitecture	Broadwell +
model number	D-1623N +
name	Xeon D-1623N +
package	FCBGA-1667 +
platform	Grangeville +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 256.00 (€ 230.40, £ 207.36, ¥ 26,452.48) +
release price (tray)	$ 256.00 (€ 230.40, £ 207.36, ¥ 26,452.48) +
series	D-1600 +
smp max ways	1 +
supported memory type	DDR4-1866 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	8 +
transistor count	3,200,000,000 +
turbo frequency (1 core)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas