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Difference between revisions of "intel/microarchitectures/rock creek"
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{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
| − | |name= | + | |name=Rock Creek |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
| Line 8: | Line 8: | ||
|process=45 nm | |process=45 nm | ||
|cores=48 | |cores=48 | ||
| + | |core name=MIC | ||
|isa=x86 | |isa=x86 | ||
| − | | | + | |isa 2=MIC |
| + | |l1i=16 KiB | ||
| + | |l1i per=core | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1d=16 KiB | ||
| + | |l1d per=core | ||
| + | |l1d desc=4-way set associative | ||
| + | |l2=256 KiB | ||
| + | |l2 per=core | ||
| + | |l2 desc=4-way set associative | ||
| + | |l3=16 KiB | ||
| + | |l3 per=tile | ||
|predecessor=Polaris | |predecessor=Polaris | ||
|predecessor link=intel/microarchitectures/polaris | |predecessor link=intel/microarchitectures/polaris | ||
| Line 15: | Line 27: | ||
|successor link=intel/microarchitectures/knights ferry | |successor link=intel/microarchitectures/knights ferry | ||
}} | }} | ||
| − | '''Rock Creek''' or the ''' Single-Chip Cloud Computer''' ('''SCC''') was the successor to {{\\|Polaris}}, a [[45 nm]] [[many-core]] microarchitecture designed by [[ | + | |
| + | '''Rock Creek''' or the ''' Single-Chip Cloud Computer''' ('''SCC''') was the successor to {{\\|Polaris}}, a [[45 nm]] [[many-core|MIC]] microarchitecture | ||
| + | :designed by [[Intel]] for high performance computing and [[many-core]] software research. | ||
| + | The SCC, like {{\\|Polaris}}, was a research project from Intel's [[Tera-scale Computing Research Program]]. | ||
| + | |||
| + | == Overview == | ||
| + | [[File:intel scc chip.jpg|left|thumb|SCC Chip]] | ||
== Architecture == | == Architecture == | ||
| − | |||
| − | == | + | === Rock Lake === |
| − | + | ||
| + | :[[File:rock lake platform.png|700px]] | ||
| + | |||
| + | |||
| + | :[[File:rock lake platform board.jpg|700px]] | ||
== Die == | == Die == | ||
| Line 45: | Line 66: | ||
=== Tile === | === Tile === | ||
| − | + | * 48,000,000 transistors | |
* 3.6 mm x 5.2 mm | * 3.6 mm x 5.2 mm | ||
** 18.7 mm² silicon area | ** 18.7 mm² silicon area | ||
Latest revision as of 07:18, 3 May 2025
| Edit Values | |
| Rock Creek µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | December 2009 |
| Process | 45 nm |
| Core Configs | 48 |
| Instructions | |
| ISA | x86, MIC |
| Cache | |
| L1I Cache | 16 KiB/core 4-way set associative |
| L1D Cache | 16 KiB/core 4-way set associative |
| L2 Cache | 256 KiB/core 4-way set associative |
| L3 Cache | 16 KiB/tile |
| Cores | |
| Core Names | MIC |
| Succession | |
Rock Creek or the Single-Chip Cloud Computer (SCC) was the successor to Polaris, a 45 nm MIC microarchitecture
The SCC, like Polaris, was a research project from Intel's Tera-scale Computing Research Program.
Contents
Overview[edit]
Architecture[edit]
Rock Lake[edit]
Die[edit]
- 45 nm process
- 1 poly, 9 Metal (Cu)
- 1,300,000,000 transistors
- 26.5 mm x 21.4 mm
- 567.1 mm² die size
- 1,567 pins LGA packages
- 970 signal pins
.png)
Tile[edit]
- 48,000,000 transistors
- 3.6 mm x 5.2 mm
- 18.7 mm² silicon area
.png)
Additional Shots[edit]
Additional die and wafer shots provided by Intel:
Bibliography[edit]
- “Single-chip Cloud Computer”. An experimental many-core processor from Intel Labs. Jim Held, Intel Fellow & Director. Tera-scale Computing Research. Symposium in Santa Clara. 2/12/10.
Documents[edit]
Facts about "Rock Creek - Microarchitectures - Intel"
| codename | Knights Ferry + |
| core count | 48 + |
| designer | Intel + |
| first launched | December 2009 + |
| full page name | intel/microarchitectures/rock creek + |
| instance of | microarchitecture + |
| instruction set architecture | x86 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Knights Ferry + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) + |