Semiconductor & Computer Engineering
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'''Cortex-A15''' (codename '''Eagle''') is the successor to the {{armh|Cortex-A9|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the {{\\|Cortex-A7}}, also the successor to the {{\\|Cortex-A9}}, target high-efficiency. | '''Cortex-A15''' (codename '''Eagle''') is the successor to the {{armh|Cortex-A9|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the {{\\|Cortex-A7}}, also the successor to the {{\\|Cortex-A9}}, target high-efficiency. | ||
| + | |||
| + | The Cortex-A15 was often combined with a number of lower power cores (e.g. {{\\|Cortex-A7}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
| + | |||
| + | == Compiler support == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Arch-Specific || Arch-Favorable | ||
| + | |- | ||
| + | | [[Arm Compiler]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code> | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code> | ||
| + | |- | ||
| + | | [[LLVM]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code> | ||
| + | |} | ||
| + | |||
| + | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior. | ||
| + | |||
| + | If the Cortex-A15 is coupled with the {{\\|Cortex-A7}} in a [[big.LITTLE]] system, GCC also supports the following option: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Tune | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mtune=cortex-a15.cortex-a7</code> | ||
| + | |} | ||
== Architecture == | == Architecture == | ||
Latest revision as of 13:40, 31 December 2018
| Edit Values | |
| Cortex-A15 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | September 8, 2010 |
| Instructions | |
| ISA | ARMv7 |
| Succession | |
Cortex-A15 (codename Eagle) is the successor to the Cortex-A9, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the Cortex-A7, also the successor to the Cortex-A9, target high-efficiency.
The Cortex-A15 was often combined with a number of lower power cores (e.g. Cortex-A7) in a big.LITTLE configuration to achieve better energy/performance.
Contents
Compiler support[edit]
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| Arm Compiler | -mcpu=cortex-a15 |
-mtune=cortex-a15
|
| GCC | -mcpu=cortex-a15 |
-mtune=cortex-a15
|
| LLVM | -mcpu=cortex-a15 |
-mtune=cortex-a15
|
One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.
If the Cortex-A15 is coupled with the Cortex-A7 in a big.LITTLE system, GCC also supports the following option:
| Compiler | Tune |
|---|---|
| GCC | -mtune=cortex-a15.cortex-a7
|
Architecture[edit]
Key changes from Cortex-A9[edit]
- 28 nm process (from 40 nm)
- Longer pipeline (15+, up from 9-12)
- 1.25x frequency (2.5 GHz, up from 2 GHz)
- 6x larger return stack size (48 entries, up from 8)
- Integer
- Hardware division support
- Hardware Fused Multiply-Accumulate
- VFPv4 (from VFPv3)
- NEONv2 (from NEON)
- Memory subsystem
- Level 1 instruction cache switched to PIPT (from VIPT)
- Level 1 instruction cache reduced to 2-way set associative (down from 4-way)
- Level 1 data cache reduced to 2-way set associative (down from 4-way)
- Added LPAE support
This list is incomplete; you can help by expanding it.
Block Diagram[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Licensees[edit]
Arm named the following companies as licensees.
| codename | Cortex-A15 + |
| designer | ARM Holdings + |
| first launched | September 8, 2010 + |
| full page name | arm holdings/microarchitectures/cortex-a15 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A15 + |