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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=September 8, 2010
 
|introduction=September 8, 2010
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|isa=ARMv7
 
|predecessor=Cortex-A9
 
|predecessor=Cortex-A9
 
|predecessor link=arm_holdings/microarchitectures/cortex-a9
 
|predecessor link=arm_holdings/microarchitectures/cortex-a9
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|successor link=arm_holdings/microarchitectures/cortex-a57
 
|successor link=arm_holdings/microarchitectures/cortex-a57
 
}}
 
}}
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'''Cortex-A15''' (codename '''Eagle''') is the successor to the {{armh|Cortex-A9|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the {{\\|Cortex-A12}} (and the {{\\|Cortex-A17|A17}}), also the successor to the {{\\|Cortex-A9}}, target high-efficiency.
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'''Cortex-A15''' (codename '''Eagle''') is the successor to the {{armh|Cortex-A9|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the {{\\|Cortex-A7}}, also the successor to the {{\\|Cortex-A9}}, target high-efficiency.
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The Cortex-A15 was often combined with a number of lower power cores (e.g. {{\\|Cortex-A7}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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== Compiler support ==
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{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[Arm Compiler]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code>
 +
|-
 +
| [[GCC]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code>
 +
|-
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| [[LLVM]] || <code>-mcpu=cortex-a15</code> || <code>-mtune=cortex-a15</code>
 +
|}
 +
 
 +
One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior.
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 +
If the Cortex-A15 is coupled with the {{\\|Cortex-A7}} in a [[big.LITTLE]] system, GCC also supports the following option:
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{| class="wikitable"
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|-
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! Compiler !! Tune
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|-
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| [[GCC]] || <code>-mtune=cortex-a15.cortex-a7</code>
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|}
  
 
== Architecture ==
 
== Architecture ==
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* [[28 nm process]] (from [[40 nm]])
 
* [[28 nm process]] (from [[40 nm]])
 
* Longer [[pipeline]] (15+, up from 9-12)
 
* Longer [[pipeline]] (15+, up from 9-12)
 +
** 1.25x frequency (2.5 GHz, up from 2 GHz)
 
* 6x larger [[return stack]] size (48 entries, up from 8)
 
* 6x larger [[return stack]] size (48 entries, up from 8)
 
* Integer
 
* Integer
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* [[VFPv4]] (from [[VFPv3]])
 
* [[VFPv4]] (from [[VFPv3]])
 
* [[NEONv2]] (from [[NEON]])
 
* [[NEONv2]] (from [[NEON]])
−
* Added {{arm|LPAE}} support
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* Memory subsystem
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** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])
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** Level 1 [[instruction cache]] reduced to 2-way set associative (down from 4-way)
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** Level 1 [[data cache]] reduced to 2-way set associative (down from 4-way)
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** Added {{arm|LPAE}} support
  
 
{{expand list}}
 
{{expand list}}

Latest revision as of 13:40, 31 December 2018

Edit Values
Cortex-A15 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionSeptember 8, 2010
Instructions
ISAARMv7
Succession

Cortex-A15 (codename Eagle) is the successor to the Cortex-A9, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The A15 is the first microarchitecture specifically designed for high-performance, whereas the Cortex-A7, also the successor to the Cortex-A9, target high-efficiency.

The Cortex-A15 was often combined with a number of lower power cores (e.g. Cortex-A7) in a big.LITTLE configuration to achieve better energy/performance.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a15 -mtune=cortex-a15
GCC -mcpu=cortex-a15 -mtune=cortex-a15
LLVM -mcpu=cortex-a15 -mtune=cortex-a15

One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.

If the Cortex-A15 is coupled with the Cortex-A7 in a big.LITTLE system, GCC also supports the following option:

Compiler Tune
GCC -mtune=cortex-a15.cortex-a7

Architecture[edit]

Key changes from Cortex-A9[edit]

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees[edit]

Arm named the following companies as licensees.

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Facts about "Cortex-A15 - Microarchitectures - ARM"
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codenameCortex-A15 +
designerARM Holdings +
first launchedSeptember 8, 2010 +
full page namearm holdings/microarchitectures/cortex-a15 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A15 +