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|process=65 nm
 
|process=65 nm
 
|process 2=45 nm
 
|process 2=45 nm
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|type=Superscalar
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|type 2=Pipelined
 +
|oooe=No
 +
|speculative=Yes
 +
|stages=13
 +
|decode=2-way
 +
|isa=ARMv7
 +
|extension=NEON
 +
|extension 2=TrustZone
 +
|extension 3=Thumb-2
 +
|extension 4=Jazelle-RCT
 +
|extension 5=VFPv3
 
|predecessor=ARM11
 
|predecessor=ARM11
 
|predecessor link=arm_holdings/microarchitectures/arm11
 
|predecessor link=arm_holdings/microarchitectures/arm11
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|successor link=arm_holdings/microarchitectures/cortex-a9
 
|successor link=arm_holdings/microarchitectures/cortex-a9
 
}}
 
}}
−
'''Cortex-A8''' is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
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'''Cortex-A8''' (codename '''Tiger''') is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.
 +
 
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[Arm Compiler]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
 +
|-
 +
| [[GCC]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
 +
|-
 +
| [[LLVM]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
 +
|}
 +
 
 +
One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior.
 +
 
 +
== Architecture ==
 +
The Cortex-A8 was the first application processor from the {{armh|Cortex}} family. It is also [[Arm]]'s first superscalar, dual-issue microprocessor.
 +
 
 +
=== Key changes from {{\\|ARM11}} ===
 +
* [[65 nm process]] (from [[90 nm]])
 +
* [[ARMv7]] (from [[ARMv6]])
 +
** Support for {{arm|NEON}} (ASIMD)
 +
** {{arm|VFPv3}} (from {{arm|VFPv2}})
 +
** {{arm|TrustZone}}
 +
** {{arm|Thumb-2}}
 +
** {{arm|Jazelle-RCT}} (Realtime Compilation Target)
 +
* ARM reported 2.0 DMIPS/MHz (up from 1.2 DMIPS/MHz)
 +
** Average IPC reported is 0.9 (based on SPECint95, EEMBC, Mediabench, and others)
 +
* First [[superscalar]] design
 +
** dual-issue (from single-issue)
 +
** in-order
 +
** 13-stage pipeline (up from 8 stages)
 +
** Targets frequency up to 1 GHz
 +
* First NEON implementation
 +
** 10-stage pipeline
 +
* Dedicated private L2 cache
 +
 
 +
=== Block Diagram ===
 +
[[File:cortex-a8 block diagram.svg|900px]]
 +
 
 +
=== Memory Hierarchy ===
 +
* Cache
 +
** L1I Cache
 +
*** 16 KiB OR 32 KiB (configurable)
 +
*** 4-way set associative
 +
*** 64 B line size
 +
*** [[Random replacement policy]]
 +
** L1D Cache
 +
*** 16 KiB OR 32 KiB (configurable)
 +
*** 4-way set associative
 +
*** 64 B line size
 +
*** [[Random replacement policy]]
 +
** L2 Cache
 +
*** 0 KiB OR 128 KiB OR 1 MiB (configurable)
 +
*** 8-way set associative
 +
*** 64 B line size
 +
*** Optional Parity and ECC
 +
 
 +
* TLB
 +
** ITLB
 +
*** 32-entry, fully-associative
 +
*** 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
 +
** DTLB
 +
*** 32-entry, fully-associative
 +
*** 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
 +
 
 +
== Licensees ==
 +
Arm named the following companies as licensees.
 +
 
 +
{{collist
 +
|count = 3
 +
|
 +
* [[Broadcom]]
 +
* [[Freescale]]
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* [[Panasonic]]
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* [[Samsung]]
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* [[STMicroelectronics]]
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* [[Texas Instruments]]
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* [[PMC-Sierra]]
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* [[ZiiLABS]]
 +
}}
 +
 
 +
== Die ==
 +
* [[65 nm process]] (LP)
 +
* Up to 650 MHz
 +
* 4 mm² (with cache)
 +
* 3 mm² (without cache)
 +
* 0.59 mW/MHz
 +
* <= 300 mW
 +
 
 +
 
 +
* [[65 nm process]] (GP)
 +
* Up to 1,000 MHz
 +
* 4 mm² (with cache)
 +
* 3 mm² (without cache)
 +
* 0.45 mW/MHz

Latest revision as of 13:30, 31 December 2018

Edit Values
Cortex-A8 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 5, 2005
Process65 nm, 45 nm
Pipeline
TypeSuperscalar, Pipelined
OoOENo
SpeculativeYes
Stages13
Decode2-way
Instructions
ISAARMv7
ExtensionsNEON, TrustZone, Thumb-2, Jazelle-RCT, VFPv3
Succession

Cortex-A8 (codename Tiger) is the successor to the ARM11, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as an IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a8 -mtune=cortex-a8
GCC -mcpu=cortex-a8 -mtune=cortex-a8
LLVM -mcpu=cortex-a8 -mtune=cortex-a8

One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.

Architecture[edit]

The Cortex-A8 was the first application processor from the Cortex family. It is also Arm's first superscalar, dual-issue microprocessor.

Key changes from ARM11[edit]

  • 65 nm process (from 90 nm)
  • ARMv7 (from ARMv6)
  • ARM reported 2.0 DMIPS/MHz (up from 1.2 DMIPS/MHz)
    • Average IPC reported is 0.9 (based on SPECint95, EEMBC, Mediabench, and others)
  • First superscalar design
    • dual-issue (from single-issue)
    • in-order
    • 13-stage pipeline (up from 8 stages)
    • Targets frequency up to 1 GHz
  • First NEON implementation
    • 10-stage pipeline
  • Dedicated private L2 cache

Block Diagram[edit]

cortex-a8 block diagram.svg

Memory Hierarchy[edit]

  • Cache
    • L1I Cache
    • L1D Cache
    • L2 Cache
      • 0 KiB OR 128 KiB OR 1 MiB (configurable)
      • 8-way set associative
      • 64 B line size
      • Optional Parity and ECC
  • TLB
    • ITLB
      • 32-entry, fully-associative
      • 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
    • DTLB
      • 32-entry, fully-associative
      • 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes

Licensees[edit]

Arm named the following companies as licensees.

Die[edit]

  • 65 nm process (LP)
  • Up to 650 MHz
  • 4 mm² (with cache)
  • 3 mm² (without cache)
  • 0.59 mW/MHz
  • <= 300 mW


  • 65 nm process (GP)
  • Up to 1,000 MHz
  • 4 mm² (with cache)
  • 3 mm² (without cache)
  • 0.45 mW/MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a8&oldid=85501"
Facts about "Cortex-A8 - Microarchitectures - ARM"
RDF feed
codenameCortex-A8 +
designerARM Holdings +
first launchedOctober 5, 2005 +
full page namearm holdings/microarchitectures/cortex-a8 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A8 +
process65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) +