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Difference between revisions of "apm/x-gene/apm883208-x2"
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|family=X-Gene | |family=X-Gene | ||
|series=X-Gene 2 | |series=X-Gene 2 | ||
+ | |turbo frequency=2,400 MHz | ||
|isa=ARMv8 | |isa=ARMv8 | ||
|isa family=ARM | |isa family=ARM | ||
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|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=90 °C | |tjunc max=90 °C | ||
+ | |predecessor=APM883208-X1 | ||
+ | |predecessor link=apm/x-gene/apm883208-x1 | ||
}} | }} | ||
'''APM883208-X2''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2014]]. Fabricated on [[TSMC]] [[28 nm process]] based on the {{apm|Shadowcat|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory. | '''APM883208-X2''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2014]]. Fabricated on [[TSMC]] [[28 nm process]] based on the {{apm|Shadowcat|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory. | ||
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{{main|apm/microarchitectures/shadowcat#Memory_Hierarchy|l1=Shadowcat § Cache}} | {{main|apm/microarchitectures/shadowcat#Memory_Hierarchy|l1=Shadowcat § Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=512 KiB |
− | |l1i cache= | + | |l1i cache=256 KiB |
− | |l1i break= | + | |l1i break=8x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |l1d cache= | + | |l1d cache=256 KiB |
− | |l1d break= | + | |l1d break=8x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=Write-through with write-combine | |l1d policy=Write-through with write-combine | ||
− | |l2 cache= | + | |l2 cache=1 MiB |
− | |l2 break= | + | |l2 break=4x256 KiB |
− | |l3 cache= | + | |l3 cache=8 MiB |
− | |l3 break= | + | |l3 break=1x8 MiB |
}} | }} | ||
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* Note: some ports are muxed | * Note: some ports are muxed | ||
+ | |||
+ | == Block diagram == | ||
+ | :[[File:208-x2 block.png|800px]] | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:408-x2-product-brief.pdf|Product Brief]] | ||
+ | * [[:File:408-x2-x-gene-2-evaluation-kit-product-brief.pdf|APM883408-X2 X-Gene 2 X-C2 Evaluation Kit]] |
Latest revision as of 01:37, 26 September 2018
Edit Values | |
APM883208-X2 | |
General Info | |
Designer | AppliedMicro |
Manufacturer | TSMC |
Model Number | APM883208-X2 |
Market | Server |
Introduction | September, 2014 (announced) March, 2015 (launched) |
General Specs | |
Family | X-Gene |
Series | X-Gene 2 |
Turbo Frequency | 2,400 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Shadowcat |
Process | 28 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 256 GiB |
Electrical | |
Vcore | 0.9 V |
VI/O | 1.8 V, 2.5 V, 3.3 V |
TDP | 35 W |
Tjunction | 0 °C – 90 °C |
Succession | |
APM883208-X2 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2014. Fabricated on TSMC 28 nm process based on the Shadowcat microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
Cache[edit]
- Main article: Shadowcat § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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- 2x I2C
- 4x UARTs
- GPIOs
- 2x SPI
- 2x SDIO 3.0
- JTAG / Trace
Network[edit]
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Networking
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- Note: some ports are muxed
Block diagram[edit]
Documents[edit]
Facts about "X-Gene 2 APM883208-X2 - AppliedMicro"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | X-Gene 2 APM883208-X2 - AppliedMicro#pcie + |
core count | 8 + |
core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
designer | AppliedMicro + |
family | X-Gene + |
first announced | September 2014 + |
first launched | March 2015 + |
full page name | apm/x-gene/apm883208-x2 + |
has ecc memory support | true + |
instance of | microprocessor + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.5 V (25 dV, 250 cV, 2,500 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | March 2015 + |
manufacturer | TSMC + |
market segment | Server + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) + |
max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
max sata ports | 6 + |
max usb ports | 2 + |
microarchitecture | Shadowcat + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | APM883208-X2 + |
name | APM883208-X2 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | X-Gene 2 + |
supported memory type | DDR3-1866 + |
tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
technology | CMOS + |
thread count | 8 + |
turbo frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |