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Difference between revisions of "apm/x-gene/apm883208-x2"
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{{apm title|X-Gene 2 APM883208-X2}}
 
{{apm title|X-Gene 2 APM883208-X2}}
−
{{chip}}
+
{{chip
 +
|name=APM883208-X2
 +
|no image=Yes
 +
|designer=AppliedMicro
 +
|manufacturer=TSMC
 +
|model number=APM883208-X2
 +
|market=Server
 +
|first announced=September, 2014
 +
|first launched=March, 2015
 +
|family=X-Gene
 +
|series=X-Gene 2
 +
|turbo frequency=2,400 MHz
 +
|isa=ARMv8
 +
|isa family=ARM
 +
|microarch=Shadowcat
 +
|process=28 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=8
 +
|thread count=8
 +
|max memory=256 GiB
 +
|v core=0.9 V
 +
|v io=1.8 V
 +
|v io 2=2.5 V
 +
|v io 3=3.3 V
 +
|tdp=35 W
 +
|tjunc min=0 °C
 +
|tjunc max=90 °C
 +
|predecessor=APM883208-X1
 +
|predecessor link=apm/x-gene/apm883208-x1
 +
}}
 
'''APM883208-X2''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2014]]. Fabricated on [[TSMC]] [[28 nm process]] based on the {{apm|Shadowcat|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
 
'''APM883208-X2''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2014]]. Fabricated on [[TSMC]] [[28 nm process]] based on the {{apm|Shadowcat|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
  
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{{main|apm/microarchitectures/shadowcat#Memory_Hierarchy|l1=Shadowcat § Cache}}
 
{{main|apm/microarchitectures/shadowcat#Memory_Hierarchy|l1=Shadowcat § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=256 KiB
+
|l1 cache=512 KiB
−
|l1i cache=128 KiB
+
|l1i cache=256 KiB
−
|l1i break=4x32 KiB
+
|l1i break=8x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1d cache=128 KiB
+
|l1d cache=256 KiB
−
|l1d break=4x32 KiB
+
|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=Write-through with write-combine
 
|l1d policy=Write-through with write-combine
−
|l2 cache=512 KiB
+
|l2 cache=1 MiB
−
|l2 break=2x256 KiB
+
|l2 break=4x256 KiB
−
|l3 cache=4 MiB
+
|l3 cache=8 MiB
−
|l3 break=1x4 MiB
+
|l3 break=1x8 MiB
 
}}
 
}}
  
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* Note: some ports are muxed
 
* Note: some ports are muxed
 +
 +
== Block diagram ==
 +
:[[File:208-x2 block.png|800px]]
 +
 +
== Documents ==
 +
* [[:File:408-x2-product-brief.pdf|Product Brief]]
 +
* [[:File:408-x2-x-gene-2-evaluation-kit-product-brief.pdf|APM883408-X2 X-Gene 2 X-C2 Evaluation Kit]]

Latest revision as of 00:37, 26 September 2018

Edit Values
APM883208-X2
General Info
DesignerAppliedMicro
ManufacturerTSMC
Model NumberAPM883208-X2
MarketServer
IntroductionSeptember, 2014 (announced)
March, 2015 (launched)
General Specs
FamilyX-Gene
SeriesX-Gene 2
Turbo Frequency2,400 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureShadowcat
Process28 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory256 GiB
Electrical
Vcore0.9 V
VI/O1.8 V, 2.5 V, 3.3 V
TDP35 W
Tjunction0 °C – 90 °C
Succession

APM883208-X2 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2014. Fabricated on TSMC 28 nm process based on the Shadowcat microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.

Cache[edit]

Main article: Shadowcat § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativeWrite-through with write-combine
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB  
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  1x8 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1866
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth27.82 GiB/s
28,487.68 MiB/s
29.871 GB/s
29,871.498 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.82 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 17
Configuration: 1x16+x1, 2x8+x1
USBRevision: 2.0
Max Ports: 2
SATARevision: 3.0
Max Ports: 6
  • 2x I2C
  • 4x UARTs
  • GPIOs
  • 2x SPI
  • 2x SDIO 3.0
  • JTAG / Trace

Network[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 4)
SGMIIYes (Ports: 1)
  • Note: some ports are muxed

Block diagram[edit]

208-x2 block.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=apm/x-gene/apm883208-x2&oldid=82841"
Facts about "X-Gene 2 APM883208-X2 - AppliedMicro"
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X-Gene 2 APM883208-X2 - AppliedMicro#pcie +
core count8 +
core voltage0.9 V (9 dV, 90 cV, 900 mV) +
designerAppliedMicro +
familyX-Gene +
first announcedSeptember 2014 +
first launchedMarch 2015 +
full page nameapm/x-gene/apm883208-x2 +
has ecc memory supporttrue +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.5 V (25 dV, 250 cV, 2,500 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateMarch 2015 +
manufacturerTSMC +
market segmentServer +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
max sata ports6 +
max usb ports2 +
microarchitectureShadowcat +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberAPM883208-X2 +
nameAPM883208-X2 +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesX-Gene 2 +
supported memory typeDDR3-1866 +
tdp35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count8 +
turbo frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +