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{{nvidia title|Carmel|arch}}
 
{{nvidia title|Carmel|arch}}
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{{microarchitecture}}
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{{microarchitecture
 +
|atype=CPU
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|name=Carmel
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|designer=Nvidia
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|manufacturer=TSMC
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|introduction=January 7, 2018
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|process=12 nm
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|cores=8
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|type=Superscalar
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|isa=ARMv8
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|feature=RAS
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|l2=2 MiB
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|l2 per=cluster
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|l3=4 MiB
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|l3 per=complex
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|predecessor=Denver 2
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|predecessor link=nvidia/microarchitectures/denver 2
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}}
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'''Carmel''' is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]].
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== Process Technology ==
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Carmel is integrated into chips fabricated on [[TSMC]] [[12 nm process]] (12FFN)
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== Architecture ==
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Nvidia disclosed very few details regarding Carmel. Carmel is a 10-wide superscalar with each core supporting dual execution mode.
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=== Key changes from {{\\|Denver 2}} ===
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* [[12 nm]] (12FFN)
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* ARMv8.2
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** ARM RAS standard support
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* Wider dispatch (10, up from 7)
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=== Memory Hierarchy ===
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* Cache
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** Parity & ECC
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** L1
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** L2
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*** 2 MiB
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**** Shared per duplex
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** L3
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*** 4 MiB
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**** Shared by entire cluster
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**** Exclusive
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=== Block Diagram ===
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==== CPU Complex ====
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[[File:nvidia carmel complex diagram.svg|600px]]
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== Overview ==
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Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
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The cores consume 500-1,500 mW per core.
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=== Performance claims ===
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{| class="wikitable"
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|-
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! SPECint 2000 Rate !! SPECint 2006
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|-
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| 2700 || 21
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|}
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== Die ==
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=== CPU Complex ===
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* 8 cores
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** 4 duplexes
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** shared L3
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* ~62.25 mm² die size area
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 +
:[[File:nvidia carmel complex.png|class=wikichip_ogimage|600px]]
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:[[File:nvidia carmel complex (annotated).png|600px]]
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=== CPU Duplex ===
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* 2 cores
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* ~11.4 mm² die size area
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:[[File:nvidia carmel duplex.png|400px]]
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:[[File:nvidia carmel duplex (annotated).png|400px]]
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=== Core ===
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* ~5.75 mm² die size area
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:[[File:nvidia carmel core.png|200px]]
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== Bibliography ==
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* IEEE Hot Chips 30 Symposium (HCS) 2018.

Latest revision as of 10:27, 30 April 2019

Edit Values
Carmel µarch
General Info
Arch TypeCPU
DesignerNvidia
ManufacturerTSMC
IntroductionJanuary 7, 2018
Process12 nm
Core Configs8
Pipeline
TypeSuperscalar
Instructions
ISAARMv8
Cache
L2 Cache2 MiB/cluster
L3 Cache4 MiB/complex
Succession

Carmel is a the successor to Denver 2, an ARM microarchitecture for Nvidia's Tegra series of SoCs.

Process Technology[edit]

Carmel is integrated into chips fabricated on TSMC 12 nm process (12FFN)

Architecture[edit]

Nvidia disclosed very few details regarding Carmel. Carmel is a 10-wide superscalar with each core supporting dual execution mode.

Key changes from Denver 2[edit]

  • 12 nm (12FFN)
  • ARMv8.2
    • ARM RAS standard support
  • Wider dispatch (10, up from 7)

Memory Hierarchy[edit]

  • Cache
    • Parity & ECC
    • L1
    • L2
      • 2 MiB
        • Shared per duplex
    • L3
      • 4 MiB
        • Shared by entire cluster
        • Exclusive

Block Diagram[edit]

CPU Complex[edit]

nvidia carmel complex diagram.svg

Overview[edit]

Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has cache coherency as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.

The cores consume 500-1,500 mW per core.

Performance claims[edit]

SPECint 2000 Rate SPECint 2006
2700 21

Die[edit]

CPU Complex[edit]

  • 8 cores
    • 4 duplexes
    • shared L3
  • ~62.25 mm² die size area
nvidia carmel complex.png


nvidia carmel complex (annotated).png

CPU Duplex[edit]

  • 2 cores
  • ~11.4 mm² die size area
nvidia carmel duplex.png


nvidia carmel duplex (annotated).png

Core[edit]

  • ~5.75 mm² die size area
nvidia carmel core.png

Bibliography[edit]

  • IEEE Hot Chips 30 Symposium (HCS) 2018.
Retrieved from "https://en.wikichip.org/w/index.php?title=nvidia/microarchitectures/carmel&oldid=89552"
Facts about "Carmel - Microarchitectures - Nvidia"
RDF feed
codenameCarmel +
core count8 +
designerNvidia +
first launchedJanuary 7, 2018 +
full page namenvidia/microarchitectures/carmel +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCarmel +
pipeline stages10 +
process12 nm (0.012 μm, 1.2e-5 mm) +