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Difference between revisions of "intel/microarchitectures/ice lake (server)"
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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=April, 2021 |
− | |process=10 nm | + | |process=10 nm + |
+ | |cores=8 | ||
+ | |cores 2=10 | ||
+ | |cores 3=12 | ||
+ | |cores 4=16 | ||
+ | |cores 5=18 | ||
+ | |cores 6=20 | ||
+ | |cores 7=24 | ||
+ | |cores 8=26 | ||
+ | |cores 9=28 | ||
+ | |cores 10=32 | ||
+ | |cores 11=36 | ||
+ | |cores 12=38 | ||
+ | |cores 13=40 | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |stages min=14 | ||
+ | |stages max=19 | ||
+ | |decode=5-way | ||
|isa=x86-64 | |isa=x86-64 | ||
+ | |l1i=32 KiB | ||
+ | |l1i per=core | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d=48 KiB | ||
+ | |l1d per=core | ||
+ | |l1d desc=12-way set associative | ||
+ | |l2=1.25 MiB | ||
+ | |l2 per=core | ||
+ | |l2 desc=20-way set associative | ||
+ | |l3=1.5 MiB | ||
+ | |l3 per=core | ||
+ | |l3 desc=12-way set associative | ||
|core name=Ice Lake SP | |core name=Ice Lake SP | ||
|core name 2=Ice Lake X | |core name 2=Ice Lake X | ||
− | |predecessor= | + | |predecessor=Cascade Lake |
− | |predecessor link=intel/microarchitectures/ | + | |predecessor link=intel/microarchitectures/cascade lake |
|successor=Sapphire Rapids | |successor=Sapphire Rapids | ||
|successor link=intel/microarchitectures/sapphire rapids | |successor link=intel/microarchitectures/sapphire rapids | ||
− | |contemporary=Ice Lake (client) | + | |contemporary=Cooper Lake |
− | |contemporary link=intel/microarchitectures/ice_lake_(client) | + | |contemporary link=intel/microarchitectures/cooper lake |
+ | |contemporary 2=Ice Lake (client) | ||
+ | |contemporary 2 link=intel/microarchitectures/ice_lake_(client) | ||
}} | }} | ||
− | '''Ice Lake''' ('''ICL''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers. | + | '''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers. |
== Codenames == | == Codenames == | ||
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| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors | | {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors | ||
|} | |} | ||
+ | |||
+ | == Release Dates == | ||
+ | [[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]] | ||
+ | Ice Lake server processors were said to launch in the first half of 2021. | ||
== Process Technology== | == Process Technology== | ||
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! Compiler !! Arch-Specific || Arch-Favorable | ! Compiler !! Arch-Specific || Arch-Favorable | ||
|- | |- | ||
− | | [[ICC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | + | | [[ICC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code> |
|- | |- | ||
− | | [[GCC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | + | | [[GCC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code> |
|- | |- | ||
− | | [[LLVM]] || <code>-march=icelake</code> || <code>-mtune=icelake</code> | + | | [[LLVM]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code> |
|- | |- | ||
− | | [[Visual Studio]] || <code>/ | + | | [[Visual Studio]] || <code>/arch=AVX512</code> || <code>/tune:?</code> |
|} | |} | ||
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| colspan="4" | Family 6 Model ? | | colspan="4" | Family 6 Model ? | ||
|- | |- | ||
− | | rowspan="2" | | + | | rowspan="2" | SP || 0 || 0x6 || 6 || A |
|- | |- | ||
− | | colspan="4" | Family 6 Model | + | | colspan="4" | Family 6 Model 106 |
|} | |} | ||
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=== Key changes from {{\\|Cascade Lake}}=== | === Key changes from {{\\|Cascade Lake}}=== | ||
− | |||
− | |||
* Enhanced "10nm+" (from [[14 nm]]) | * Enhanced "10nm+" (from [[14 nm]]) | ||
+ | * {{\\|Sunny Cove|Sunny Cove core}} | ||
+ | ** ''See {{\\|Sunny Cove}} for microarchitectural details and changes'' | ||
* I/O | * I/O | ||
** PCIe 4.0 (from PCIe 3.0) | ** PCIe 4.0 (from PCIe 3.0) | ||
Line 75: | Line 112: | ||
** Octa-channel (up from hexa-channel) | ** Octa-channel (up from hexa-channel) | ||
** 3200 MT/s (up from 2933 MT/s) | ** 3200 MT/s (up from 2933 MT/s) | ||
+ | ** Optane DC DIMMs | ||
+ | *** Apache Pass '''→''' Barlow Pass | ||
* Platform | * Platform | ||
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} | ** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}} | ||
* Packaging | * Packaging | ||
** 4189-contact flip-chip LGA (up from 3647 contacts) | ** 4189-contact flip-chip LGA (up from 3647 contacts) | ||
+ | {{expand list}} | ||
====New instructions ==== | ====New instructions ==== | ||
− | Ice Lake introduced a number of {{x86|extensions|new instructions}} | + | Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details. |
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== All Ice Lake Chips == | == All Ice Lake Chips == |
Latest revision as of 18:41, 26 March 2024
Edit Values | |
Ice Lake (server) µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | April, 2021 |
Process | 10 nm + |
Core Configs | 8, 10, 12, 16, 18, 20, 24, 26, 28, 32, 36, 38, 40 |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way |
Instructions | |
ISA | x86-64 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 48 KiB/core 12-way set associative |
L2 Cache | 1.25 MiB/core 20-way set associative |
L3 Cache | 1.5 MiB/core 12-way set associative |
Cores | |
Core Names | Ice Lake SP, Ice Lake X |
Succession | |
Contemporary | |
Cooper Lake Ice Lake (client) |
Ice Lake (ICL, ICX) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.
Contents
Codenames[edit]
Core | Abbrev | Target |
---|---|---|
Ice Lake X | ICL-X | High-end desktops & enthusiasts market |
Ice Lake W | ICL-W | Enterprise/Business workstations |
Ice Lake SP | ICL-SP | Server Scalable Processors |
Release Dates[edit]
![](/w/images/thumb/9/93/intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png/300px-intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png)
Cooper Lake and Ice Lake roadmap.
Ice Lake server processors were said to launch in the first half of 2021.
Process Technology[edit]
- See also: Ice Lake (client) § Process Technology
Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.
Compiler support[edit]
Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=icelake-server |
-mtune=icelake-server
|
GCC | -march=icelake-server |
-mtune=icelake-server
|
LLVM | -march=icelake-server |
-mtune=icelake-server
|
Visual Studio | /arch=AVX512 |
/tune:?
|
CPUID[edit]
Core | Extended Family |
Family | Extended Model |
Model |
---|---|---|---|---|
? | 0 | 0x6 | 0x? | ? |
Family 6 Model ? | ||||
SP | 0 | 0x6 | 6 | A |
Family 6 Model 106 |
Architecture[edit]
Key changes from Cascade Lake[edit]
- Enhanced "10nm+" (from 14 nm)
- Sunny Cove core
- See Sunny Cove for microarchitectural details and changes
- I/O
- PCIe 4.0 (from PCIe 3.0)
- Memory
- Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
- Octa-channel (up from hexa-channel)
- 3200 MT/s (up from 2933 MT/s)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- 4189-contact flip-chip LGA (up from 3647 contacts)
This list is incomplete; you can help by expanding it.
New instructions[edit]
Ice Lake introduced a number of new instructions. See Sunny Cove § New Instructions for details.
All Ice Lake Chips[edit]
List of Ice Lake Processors | |||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Main processor | Frequency/Turbo | Mem | Major Feature Diff | ||||||||||||||||||||||
Model | Launched | Price | Family | Core Name | Cores | Threads | L2$ | L3$ | TDP | Frequency | Max Turbo | Max Mem | Turbo | SMT | |||||||||||
Uniprocessors | |||||||||||||||||||||||||
Multiprocessors (2-way) | |||||||||||||||||||||||||
Multiprocessors (4-way) | |||||||||||||||||||||||||
Multiprocessors (8-way) | |||||||||||||||||||||||||
Count: 0 |
Facts about "Ice Lake (server) - Microarchitectures - Intel"
codename | Ice Lake (server) + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/ice lake (server) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (server) + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |