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Difference between revisions of "hisilicon/kunpeng/920-6426"
< hisilicon‎ | kunpeng

 
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{{hisilicon title|Hi1620}}
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{{hisilicon title|Kunpeng 920-6426}}
 
{{chip
 
{{chip
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|future=Yes
+
|name=Kunpeng 920-6426
−
|name=Hi1620
+
|image=kunpeng 920 (front).png
−
|no image=Yes
 
 
|designer=HiSilicon
 
|designer=HiSilicon
 
|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|model number=Hi1620
+
|model number=920-6426
 
|market=Server
 
|market=Server
 
|first announced=September, 2018
 
|first announced=September, 2018
−
|first launched=September, 2018
+
|first launched=January 7, 2019
 
|family=Hi16xx
 
|family=Hi16xx
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|frequency=3,000 MHz
+
|series=920
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|isa=ARMv8
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|frequency=2,600 MHz
 +
|isa=ARMv8.2
 
|isa family=ARM
 
|isa family=ARM
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|microarch=Cortex-A73
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|microarch=TaiShan v110
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|core name=Cortex-A73
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|core name=TaiShan v110
 +
|transistors=20,000,000,000
 
|technology=CMOS
 
|technology=CMOS
 +
|mcp=Yes
 +
|die count=3
 
|word size=64 bit
 
|word size=64 bit
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|core count=48
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|core count=64
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|thread count=48
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|thread count=64
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|max cpus=2
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|max memory=2 TiB
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|max memory=512 GiB
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|max cpus=4
 +
|tdp=195 W
 
}}
 
}}
−
'''Hi1620''' is a planned [[octatetraconta-core]] {{arch|64}} [[ARM]] server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by [[TSMC]] on a [[? nm process]], this chip incorporates 48 {{armh|Cortex-A73}} cores operating at 3 GHz. The Hi1620 supports up to 512 GiB of quad-channel DDR4-2400 memory.
+
[[File:hi1620 exhibit sign.jpg|thumb|right|Hi1620 on exhibit.]]
−
 
+
'''Kunpeng 920-6426''' is a [[tetrahexaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by [[HiSilicon]] in early 2019. Fabricated by [[TSMC]] on a [[7 nm process|7nm HPC process]] based on the {{hisilicon|TaiSHan v110|l=arch}} microarchitecture, this chip incorporates 64 cores operating at 2.6 GHz with a TDP of 180 W. This chip supports up to 2 TiB of octa-channel DDR4-2933 memory.
−
 
 
−
{{unknown features}}
 
  
 
== Cache ==
 
== Cache ==
−
{{main|arm holdings/microarchitectures/cortex-a72#Memory_Hierarchy|l1=Cortex-A72 § Cache}}
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{{main|hisilicon/microarchitectures/taishan_v110#Memory_Hierarchy|l1=TaiShan v110 § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=3.75 MiB
+
|l1 cache=8 MiB
−
|l1i cache=2.25 MiB
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|l1i cache=4 MiB
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|l1i break=48x48 KiB
+
|l1i break=64x64 KiB
−
|l1i desc=8-way set associative
+
|l1d cache=4 MiB
−
|l1d cache=1.5 MiB
+
|l1d break=64x64 KiB
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|l1d break=48x32 KiB
+
|l2 cache=32 MiB
−
|l1d desc=8-way set associative
+
|l2 break=64x512 KiB
−
|l2 cache=12 MiB
+
|l3 cache=64 MiB
−
|l2 break=48x256 KiB
+
|l3 break=64x1 MiB
−
|l2 desc=8-way set associative
 
−
|l3 cache=48 MiB
 
−
|l3 break=48x1 MiB
 
−
|l3 desc=16-way set associative
 
 
}}
 
}}
  
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2400
+
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
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|max mem=512 GiB
+
|max mem=2 TiB
 
|controllers=1
 
|controllers=1
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|channels=4
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|channels=8
 
|width=64 bit
 
|width=64 bit
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|max bandwidth=71.53 GiB/s
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|max bandwidth=190.7 GiB/s
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|bandwidth schan=17.88 GiB/s
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|bandwidth schan=23.84 GiB/s
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|bandwidth dchan=35.76 GiB/s
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|bandwidth dchan=47.68 GiB/s
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|bandwidth qchan=71.53 GiB/s
+
|bandwidth qchan=95.37 GiB/s
 +
|bandwidth ochan=190.7 GiB/s
 
}}
 
}}
  
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{{expansions entry
 
{{expansions entry
 
|type=PCIe
 
|type=PCIe
−
|pcie revision=3.0
+
|pcie revision=4.0
−
|pcie lanes=16
+
|pcie lanes=40
−
|pcie config=2x8
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|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=4
 +
}}
 +
{{expansions entry
 +
|type=SATA
 +
|sata revision=3.0
 +
|sata ports=2
 +
}}
 
}}
 
}}
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=No
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=No
 +
|crc32=Yes
 +
|crypto=Yes
 +
|fp=No
 +
|fp16=Yes
 +
|profile=No
 +
|ras=Yes
 +
|simd=No
 +
|rdm=No
 
}}
 
}}
  
 
== Utilizing devices ==
 
== Utilizing devices ==
 
* [[used by::HiSilicon D06]]
 
* [[used by::HiSilicon D06]]
 +
* [[used by::TaiShan 2280]]
 +
* [[used by::TaiShan 5280]]
 +
* [[used by::TaiShan 5290]]
 +
* [[used by::TaiShan X6000]]
  
 
{{expand list}}
 
{{expand list}}

Latest revision as of 01:25, 15 February 2020

Edit Values
Kunpeng 920-6426
kunpeng 920 (front).png
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model Number920-6426
MarketServer
IntroductionSeptember, 2018 (announced)
January 7, 2019 (launched)
General Specs
FamilyHi16xx
Series920
Frequency2,600 MHz
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureTaiShan v110
Core NameTaiShan v110
Transistors20,000,000,000
TechnologyCMOS
MCPYes (3 dies)
Word Size64 bit
Cores64
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP195 W
Hi1620 on exhibit.

Kunpeng 920-6426 is a tetrahexaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in early 2019. Fabricated by TSMC on a 7nm HPC process based on the TaiSHan v110 microarchitecture, this chip incorporates 64 cores operating at 2.6 GHz with a TDP of 180 W. This chip supports up to 2 TiB of octa-channel DDR4-2933 memory.

Cache[edit]

Main article: TaiShan v110 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$8 MiB
8,192 KiB
8,388,608 B
L1I$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L1D$4 MiB
4,096 KiB
4,194,304 B
64x64 KiB  
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  64x512 KiB  
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  64x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels8
Width64 bit
Max Bandwidth190.7 GiB/s
195,276.8 MiB/s
204.763 GB/s
204,762.566 MB/s
0.186 TiB/s
0.205 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Octa 190.7 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 40
Configuration: x16, x8, x4
USBRevision: 3.0
Max Ports: 4
SATARevision: 3.0
Max Ports: 2

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FP16ARMv8.2-A half-precision floating-point extension
RASReliability, Availability, and Serviceability extension

Utilizing devices[edit]

  • HiSilicon D06
  • TaiShan 2280
  • TaiShan 5280
  • TaiShan 5290
  • TaiShan X6000

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/920-6426&oldid=95965"
Facts about "Kunpeng 920-6426 - HiSilicon"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Kunpeng 920-6426 - HiSilicon#pcie +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
core count48 +
core nameCortex-A73 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedSeptember 2018 +
first launchedSeptember 2018 +
full page namehisilicon/kunpeng/920-6426 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size3,840 KiB (3,932,160 B, 3.75 MiB) +
l1d$ description8-way set associative +
l1d$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description8-way set associative +
l1i$ size2,304 KiB (2,359,296 B, 2.25 MiB) +
l2$ description8-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description16-way set associative +
l3$ size48 MiB (49,152 KiB, 50,331,648 B, 0.0469 GiB) +
ldate3000 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels4 +
microarchitectureCortex-A73 +
model numberHi1620 +
nameHi1620 +
smp max ways2 +
supported memory typeDDR4-2400 +
technologyCMOS +
thread count48 +
used byHiSilicon D06 +
word size64 bit (8 octets, 16 nibbles) +