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Difference between revisions of "cavium/thunderx2/cn9965"
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|part number 5=CN9965-2100LG4077-Y21-G | |part number 5=CN9965-2100LG4077-Y21-G | ||
|part number 6=CN9965-2000LG4077-Y21-G | |part number 6=CN9965-2000LG4077-Y21-G | ||
+ | |part number 7=CN9965-1800LG4077-Y21-G | ||
|market=Server | |market=Server | ||
|first announced=May 7, 2018 | |first announced=May 7, 2018 | ||
Line 20: | Line 21: | ||
|frequency 3=2,100 MHz | |frequency 3=2,100 MHz | ||
|frequency 4=2,200 MHz | |frequency 4=2,200 MHz | ||
+ | |frequency 5=2,300 MHz | ||
+ | |frequency 6=2,400 MHz | ||
+ | |frequency 7=2,500 MHz | ||
|isa=ARMv8.1 | |isa=ARMv8.1 | ||
|isa family=ARM | |isa family=ARM | ||
Line 49: | Line 53: | ||
|l3 cache=20 MiB | |l3 cache=20 MiB | ||
|l3 break=20x1 MiB | |l3 break=20x1 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | The 1.8 GHz model only supports quad-channel memory while all other models support hexa-channel memory. | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=56 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | |pcie config 4=x1 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=SATA | ||
+ | |sata revision=3 | ||
+ | |sata ports=2 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=3 | ||
+ | |usb ports=2 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=No | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=No | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |trustzone=Yes | ||
+ | |jazelle=No | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | |pmuv3=Yes | ||
+ | |crc32=Yes | ||
+ | |crypto=Yes | ||
+ | |fp=Yes | ||
+ | |fp16=No | ||
+ | |profile=No | ||
+ | |ras=No | ||
+ | |simd=Yes | ||
+ | |rdm=No | ||
}} | }} |
Latest revision as of 23:14, 3 December 2018
Edit Values | |
ThunderX2 CN9965 | |
General Info | |
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN9965 |
Part Number | CN9965-2500LG4077-Y21-G, CN9965-2400LG4077-Y21-G, CN9965-2300LG4077-Y21-G, CN9965-2200LG4077-Y21-G, CN9965-2100LG4077-Y21-G, CN9965-2000LG4077-Y21-G, CN9965-1800LG4077-Y21-G |
Market | Server |
Introduction | May 7, 2018 (announced) May 7, 2018 (launched) |
General Specs | |
Family | ThunderX2 |
Frequency | 1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz, 2,300 MHz, 2,400 MHz, 2,500 MHz |
Microarchitecture | |
ISA | ARMv8.1 (ARM) |
Microarchitecture | Vulcan |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 20 |
Threads | 40 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Packaging | |
Package | FCLGA-4077 (LGA) |
Contacts | 4077 |
ThunderX2 CN9965 is a 64-bit icosa-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9965 operates between 1.8 GHz and 2.5 GHz and supports up to quad-/hexa-channel DDR4-2666 memory.
Contents
Cache[edit]
- Main article: Vulcan § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
The 1.8 GHz model only supports quad-channel memory while all other models support hexa-channel memory.
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Facts about "ThunderX2 CN9965 - Cavium"
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) +, 2,100 MHz (2.1 GHz, 2,100,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
core count | 20 + |
designer | Cavium + |
family | ThunderX2 + |
first announced | May 7, 2018 + |
first launched | May 7, 2018 + |
full page name | cavium/thunderx2/cn9965 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8.1 + |
isa family | ARM + |
l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 5 MiB (5,120 KiB, 5,242,880 B, 0.00488 GiB) + |
l3$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
ldate | May 7, 2018 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Vulcan + |
model number | CN9965 + |
name | ThunderX2 CN9965 + |
package | FCLGA-4077 + |
part number | CN9965-2500LG4077-Y21-G +, CN9965-2400LG4077-Y21-G +, CN9965-2300LG4077-Y21-G +, CN9965-2200LG4077-Y21-G +, CN9965-2100LG4077-Y21-G + and CN9965-2000LG4077-Y21-G + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
smp max ways | 2 + |
supported memory type | DDR4-2666 + |
technology | CMOS + |
thread count | 40 + |
word size | 64 bit (8 octets, 16 nibbles) + |