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Difference between revisions of "intel/core m/m3-8114y"
< intel‎ | core m

 
(14 intermediate revisions by 3 users not shown)
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|locked=Yes
 
|locked=Yes
 
|frequency=1,500 MHz
 
|frequency=1,500 MHz
−
|turbo frequency1=2,600 MHz
 
 
|bus type=OPI
 
|bus type=OPI
 
|bus rate=4 GT/s
 
|bus rate=4 GT/s
Line 19: Line 18:
 
|isa family=x86
 
|isa family=x86
 
|microarch=Cannon Lake
 
|microarch=Cannon Lake
−
|chipset=Cannon Point
 
 
|core name=Cannon Lake Y
 
|core name=Cannon Lake Y
 
|core family=6
 
|core family=6
−
|core model=102
 
 
|process=10 nm
 
|process=10 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=2
 
|core count=2
 
|thread count=4
 
|thread count=4
 +
|max memory=16 GiB
 
|max cpus=1
 
|max cpus=1
−
|max memory=16 GiB
 
−
|tdp=4.5 W
 
 
}}
 
}}
−
'''Core M3-8114Y''' is a {{arch|64}} [[dual-core]] low-end performance ultra-low power [[x86]] mobile microprocessor introduced by [[Intel]] in early [[2018]]. This chip, which is based on the {{intel|Cannon Lake|l=arch}} microarchitecture, is fabricated on Intel's [[10 nm process]]. The M3-8114Y operates at 1.5 GHz with a TDP of 4.5 W supporting a {{intel|Turbo Boost}} frequency of 2.6 GHz. The processor supports up to 16 GiB of dual-channel LPDDR4X-2133 memory and incorporates Intel's {{intel|HD Graphics 7??}} [[IGP]] operating at ? MHz with a burst frequency of ? MHz.
+
'''Core M3-8114Y''' is a {{arch|64}} [[dual-core]] low-end performance ultra-low power [[x86]] mobile microprocessor expected to be introduced by [[Intel]] in mid [[2018]]. This chip, which is based on the {{intel|Cannon Lake|l=arch}} microarchitecture, is fabricated on [[Intel's 10 nm process]]. The M3-8114Y operates at 1.5 GHz with a TDP of 5 W. The processor supports up to 16 GiB of dual-channel ? memory and incorporates Intel's {{intel|UHD Graphics ?}} [[IGP]] operating at ? MHz with a burst frequency of ? MHz.
  
  
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== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/cannon_lake#Memory_Hierarchy|l1=Cannon Lake § Cache}}
+
{{empty section}}
−
{{cache size
 
−
|l1 cache=128 KiB
 
−
|l1i cache=64 KiB
 
−
|l1i break=2x32 KiB
 
−
|l1i desc=8-way set associative
 
−
|l1d cache=64 KiB
 
−
|l1d break=2x32 KiB
 
−
|l1d desc=8-way set associative
 
−
|l1d policy=write-back
 
−
|l2 cache=512 KiB
 
−
|l2 break=2x256 KiB
 
−
|l2 desc=4-way set associative
 
−
|l2 policy=write-back
 
−
|l3 cache=4 MiB
 
−
|l3 break=2x2 MiB
 
−
|l3 desc=16-way set associative
 
−
|l3 policy=write-back
 
−
}}
 
  
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=LPDDR4-2133
 
−
|type 2=LPDDR4X-2133
 
 
|ecc=No
 
|ecc=No
 
|max mem=16 GiB
 
|max mem=16 GiB
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== Graphics ==
 
== Graphics ==
 
{{integrated graphics
 
{{integrated graphics
−
| gpu                = HD Graphics 7??
+
| gpu                = UHD Graphics ?
 
| device id          =  
 
| device id          =  
 
| designer            = Intel
 
| designer            = Intel
−
| execution units    = 40?
+
| execution units    = ?
 
| max displays        = 3
 
| max displays        = 3
 
| max memory          = 16 GiB
 
| max memory          = 16 GiB
−
| frequency          = 300? MHz
+
| frequency          = 300 MHz
 
| max frequency      = ? MHz
 
| max frequency      = ? MHz
  
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| directx ver        = 12
 
| directx ver        = 12
−
| opengl ver        = 4.5
+
| opengl ver        = 4.4
 
| opencl ver        = 2.0
 
| opencl ver        = 2.0
−
| hdmi ver          = 2.0?
+
| hdmi ver          = 1.4a
 
| dp ver            = 1.2
 
| dp ver            = 1.2
 
| edp ver            = 1.4
 
| edp ver            = 1.4
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| intel clear video    = Yes
 
| intel clear video    = Yes
 
| intel clear video hd = Yes
 
| intel clear video hd = Yes
−
}}<!--
+
}}
−
{{cannon lake hardware accelerated video table|col=1}}-->
+
{{amber lake hardware accelerated video table|col=1}}
  
 
== Features ==  
 
== Features ==  
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|x8664=Yes
 
|x8664=Yes
 
|nx=Yes
 
|nx=Yes
−
|3dnow=No
 
−
|e3dnow=No
 
 
|mmx=Yes
 
|mmx=Yes
 
|emmx=Yes
 
|emmx=Yes
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
 
+
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
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|aes=Yes
 
|aes=Yes
 
|rdrand=Yes
 
|rdrand=Yes
−
|sha=No
+
|sha=Yes
 
|xop=No
 
|xop=No
 
|adx=Yes
 
|adx=Yes
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|flex=Yes
 
|flex=Yes
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 
|isrt=Yes
 
|isrt=Yes
 
|sba=No
 
|sba=No
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|securekey=Yes
 
|securekey=Yes
 
|osguard=Yes
 
|osguard=Yes
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 
|smartmp=No
 
|smartmp=No
 
|powernow=No
 
|powernow=No
 +
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}

Latest revision as of 06:08, 17 April 2020

Edit Values
M3-8114Y
General Info
DesignerIntel
ManufacturerIntel
Model NumberM3-8114Y
MarketMobile
ShopAmazon
General Specs
FamilyCore M3
SeriesM3-8000
LockedYes
Frequency1,500 MHz
Bus typeOPI
Bus rate4 GT/s
Clock multiplier15
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCannon Lake
Core NameCannon Lake Y
Core Family6
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads4
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Core M3-8114Y is a 64-bit dual-core low-end performance ultra-low power x86 mobile microprocessor expected to be introduced by Intel in mid 2018. This chip, which is based on the Cannon Lake microarchitecture, is fabricated on Intel's 10 nm process. The M3-8114Y operates at 1.5 GHz with a TDP of 5 W. The processor supports up to 16 GiB of dual-channel ? memory and incorporates Intel's UHD Graphics ? IGP operating at ? MHz with a burst frequency of ? MHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes10
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUUHD Graphics ?
DesignerIntel
Execution Units?
"?" is not a number.
Max Displays3
Max Memory16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency? MHz
"? MHz" is not a number.
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4096x2304 @24 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.4
HDMI1.4a
Additional Features
Intel Quick Sync Video
Intel InTru 3D
Intel Clear Video
Intel Clear Video HD

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m3-8114y&oldid=96659"
Facts about "Core M3-8114Y - Intel"
RDF feed
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus typeOPI +
chipsetCannon Point +
clock multiplier15 +
core count2 +
core family6 +
core model102 +
core nameCannon Lake Y +
designerIntel +
familyCore M3 +
full page nameintel/core m/m3-8114y +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
ldate3000 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
microarchitectureCannon Lake +
model numberM3-8114Y +
nameM3-8114Y +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesM3-8000 +
smp max ways1 +
tdp4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +