Semiconductor & Computer Engineering
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Difference between revisions of "Template:interconnect arch"
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| − | < | + | <table class="guidebox"> |
| − | < | + | <tr><td colspan="2">{{Navbar|Template:interconnect_arch|text=|mini=1|style=float:left;}}</td></tr> |
| − | < | + | <tr><td class="header-main" colspan="2">Interconnect<br>Architectures</td></tr> |
| + | <tr><td colspan="2" style="text-align: center;">[[File:interconnect.svg|225px|link=interconnect architecture]]</td></tr> | ||
| + | <tr><td class="header" colspan="2">Concepts</td></tr> | ||
| + | <tr><td colspan="2"> | ||
| + | * [[Network On A Chip]] | ||
* [[System Bus]] | * [[System Bus]] | ||
| − | + | </td></tr> | |
| − | < | + | <tr><td class="header" colspan="2">General</td></tr> |
| + | <tr><td colspan="2"> | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
| | | | ||
* [[accelerated graphics port|AGP]] | * [[accelerated graphics port|AGP]] | ||
| − | * [[CCIX]] | + | * [[CAPI]] |
| + | * [[ccix|CCIX]] | ||
| + | * {{cavium|CCPI}} | ||
| + | * {{ibm|DMI}} (IBM) | ||
| + | * {{intel|DMI}} (Intel) | ||
* [[extended industry standard architecture|EISA]] | * [[extended industry standard architecture|EISA]] | ||
* [[Gen-Z]] | * [[Gen-Z]] | ||
| + | * {{hisilicon|Hydra}} | ||
* [[hypertransport|HT]] | * [[hypertransport|HT]] | ||
* {{amd|infinity fabric|IF}} | * {{amd|infinity fabric|IF}} | ||
* [[industry standard architecture|ISA]] | * [[industry standard architecture|ISA]] | ||
| + | * {{tsmc|LIPINCON}} | ||
* [[micro channel|Micro Channel]] | * [[micro channel|Micro Channel]] | ||
* [[Multibus]] | * [[Multibus]] | ||
* {{nvidia|NVLink}} | * {{nvidia|NVLink}} | ||
| − | |||
* [[peripheral component interconnect|PCI]] | * [[peripheral component interconnect|PCI]] | ||
* [[peripheral component interconnect express|PCIe]] | * [[peripheral component interconnect express|PCIe]] | ||
| Line 30: | Line 40: | ||
* [[vesa local bus|VLB]] | * [[vesa local bus|VLB]] | ||
}} | }} | ||
| − | < | + | </td></tr> |
| + | <tr><td class="header" colspan="2">Peripheral</td></tr> | ||
| + | <tr><td colspan="2"> | ||
* [[1-wire|1-Wire]] | * [[1-wire|1-Wire]] | ||
* [[access.bus|ACCESS.bus]] | * [[access.bus|ACCESS.bus]] | ||
| Line 40: | Line 52: | ||
* [[RS-423]] | * [[RS-423]] | ||
* [[UNI/O bus]] | * [[UNI/O bus]] | ||
| − | < | + | </td></tr> |
| + | <tr><td class="header" colspan="2">Storage Devices</td></tr> | ||
| + | <tr><td colspan="2"> | ||
* [[nvm express|NVMe]] | * [[nvm express|NVMe]] | ||
* [[parallel ata|PATA]] | * [[parallel ata|PATA]] | ||
| Line 47: | Line 61: | ||
* [[serial storage architecture|SSA]] | * [[serial storage architecture|SSA]] | ||
* [[small computer system interface|SCSI]] | * [[small computer system interface|SCSI]] | ||
| − | < | + | </td></tr> |
| + | <tr><td class="header" colspan="2">Audio Devices</td></tr> | ||
| + | <tr><td colspan="2"> | ||
* [[inter-ic sound|I²S]] | * [[inter-ic sound|I²S]] | ||
* [[s/pdif|S/PDIF]] | * [[s/pdif|S/PDIF]] | ||
| − | < | + | </td></tr> |
| − | </ | + | </table> |
Latest revision as of 09:14, 1 July 2024
| Interconnect Architectures | |
 | |
| Concepts | |
| General | |
| Peripheral | |
| Storage Devices | |
| Audio Devices | |