From WikiChip
Difference between revisions of "intel/xeon d/d-2183it"
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|tdp=100 W | |tdp=100 W | ||
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+ | |tcase max=90 °C | ||
|package module 1={{packages/intel/fcbga-2518}} | |package module 1={{packages/intel/fcbga-2518}} | ||
}} | }} |
Latest revision as of 00:08, 8 February 2018
Edit Values | |||||||
Xeon D-2183IT | |||||||
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General Info | |||||||
Designer | Intel | ||||||
Manufacturer | Intel | ||||||
Model Number | D-2183IT | ||||||
Part Number | FH8067303782501 | ||||||
S-Spec | SR3ZQ | ||||||
Market | Server, Embedded | ||||||
Introduction | February 7, 2018 (announced) February 7, 2018 (launched) | ||||||
Release Price | $1764.00 | ||||||
Shop | Amazon | ||||||
General Specs | |||||||
Family | Xeon D | ||||||
Series | D-2000 | ||||||
Locked | Yes | ||||||
Frequency | 2,200 MHz | ||||||
Turbo Frequency | 3,000 MHz (1 core) | ||||||
Bus type | DMI 3.0 | ||||||
Bus rate | 4 × 8 GT/s | ||||||
Clock multiplier | 22 | ||||||
Microarchitecture | |||||||
ISA | x86-64 (x86) | ||||||
Microarchitecture | Skylake (server) | ||||||
Core Name | Skylake DE | ||||||
Core Stepping | M1 | ||||||
Process | 14 nm | ||||||
Technology | CMOS | ||||||
MCP | Yes (2 dies) | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 32 | ||||||
Max Memory | 512 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
TDP | 100 W | ||||||
Tcase | 0 °C – 90 °C | ||||||
Packaging | |||||||
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Xeon D-2183IT is a 64-bit 16-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.2 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 100 W. The D-2183IT supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory. This model is part of Skylake DE's Network Edge and Storage SKUs.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
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Expansion Options |
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Networking[edit]
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Networking
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | ||
Normal | 2,200 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz |
AVX2 | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | |
AVX512 | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,000 MHz | 2,000 MHz | 2,000 MHz | 2,000 MHz |
Facts about "Xeon D-2183IT - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-2183IT - Intel#package + and Xeon D-2183IT - Intel#pcie + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 22 + |
core count | 16 + |
core name | Skylake DE + |
core stepping | M1 + |
designer | Intel + |
die count | 2 + |
family | Xeon D + |
first announced | February 7, 2018 + |
first launched | February 7, 2018 + |
full page name | intel/xeon d/d-2183it + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | February 7, 2018 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max hsio lanes | 20 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) + |
max memory channels | 4 + |
microarchitecture | Skylake (server) + |
model number | D-2183IT + |
name | Xeon D-2183IT + |
number of avx-512 execution units | 1 + |
package | FCBGA-2518 + |
part number | FH8067303782501 + |
part of | Network Edge and Storage SKUs + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,764.00 (€ 1,587.60, £ 1,428.84, ¥ 182,274.12) + |
s-spec | SR3ZQ + |
series | D-2000 + |
smp max ways | 1 + |
supported memory type | DDR4-2400 + |
tdp | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |