Difference between revisions of "intel/xeon d/d-2191"

	Edit Values
	Xeon D-2191
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	D-2191
Market	Server, Embedded
Introduction	February 7, 2018 (announced); February 7, 2018 (launched)
Release Price	$2406
Shop	Amazon
	General Specs
Family	Xeon D
Series	D-2000
Locked	Yes
Frequency	1,600 MHz
Turbo Frequency	3,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	16
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Core Name	Skylake DE
Core Stepping	M1
Process	14 nm
Technology	CMOS
MCP	Yes (2 dies)
Word Size	64 bit
Cores	18
Threads	36
Max Memory	512 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	86 W
	Packaging
Package	FCBGA-2518 (BGA)
Dimension	45 mm x 52.5 mm
Contacts	2518

Latest revision as of 22:46, 7 February 2018

Xeon D-2191 is a 64-bit 18-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 1.6 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 86 W. The D-2191 supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory. This model is part of Skylake DE's Edge Server and Cloud SKUs.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.125 MiB

1,152 KiB
1,179,648 B

L1I$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative
L1D$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative	write-back

L2$

18 MiB

18,432 KiB
18,874,368 B
0.0176 GiB

		18x1 MiB	16-way set associative	write-back

L3$

24.75 MiB

25,344 KiB
25,952,256 B
0.0242 GiB

		18x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2400
Supports ECC	Yes
Max Mem	512 GiB
Controllers	2
Channels	4
Max Bandwidth	71.53 GiB/s 73,246.72 MiB/s 76.805 GB/s 76,804.753 MB/s 0.0699 TiB/s 0.0768 TB/s
Bandwidth	Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s
Physical Address (PAE)	46 bit

Expansions[edit]

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 32
	Configuration: x16, x8, x4

HSIO

Max Lanes: 20

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit (1 Unit)
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
VMD	Volume Management Device
IPT	Identity Protection Technology

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18
Normal	1,600 MHz	3,000 MHz	3,000 MHz	2,800 MHz	2,800 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,500 MHz	2,500 MHz	2,500 MHz	2,500 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,200 MHz	2,200 MHz
AVX2		2,900 MHz	2,900 MHz	2,700 MHz	2,700 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,500 MHz	2,500 MHz	2,500 MHz	2,500 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,200 MHz	2,200 MHz
AVX512		2,800 MHz	2,800 MHz	2,600 MHz	2,600 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz	1,900 MHz	1,900 MHz	1,900 MHz	1,900 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz

@@ Line 234: / Line 234: @@
 |freq_avx2_17=2,200 MHz
 |freq_avx2_18=2,200 MHz
+|freq_avx512_1=2,800 MHz
+|freq_avx512_2=2,800 MHz
+|freq_avx512_3=2,600 MHz
+|freq_avx512_4=2,600 MHz
+|freq_avx512_5=2,300 MHz
+|freq_avx512_6=2,300 MHz
+|freq_avx512_7=2,300 MHz
+|freq_avx512_8=2,300 MHz
+|freq_avx512_9=1,900 MHz
+|freq_avx512_10=1,900 MHz
+|freq_avx512_11=1,900 MHz
+|freq_avx512_12=1,900 MHz
+|freq_avx512_13=1,700 MHz
+|freq_avx512_14=1,700 MHz
+|freq_avx512_15=1,700 MHz
+|freq_avx512_16=1,700 MHz
+|freq_avx512_17=1,700 MHz
+|freq_avx512_18=1,700 MHz
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-2191 - Intel#package + and Xeon D-2191 - Intel#pcie +
base frequency	1,600 MHz (1.6 GHz, 1,600,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	16 +
core count	18 +
core name	Skylake DE +
core stepping	M1 +
designer	Intel +
die count	2 +
family	Xeon D +
first announced	February 7, 2018 +
first launched	February 7, 2018 +
full page name	intel/xeon d/d-2191 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	576 KiB (589,824 B, 0.563 MiB) +
l1i$ description	8-way set associative +
l1i$ size	576 KiB (589,824 B, 0.563 MiB) +
l2$ description	16-way set associative +
l2$ size	18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description	11-way set associative +
l3$ size	24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldate	February 7, 2018 +
main image	+
manufacturer	Intel +
market segment	Server + and Embedded +
max cpu count	1 +
max hsio lanes	20 +
max memory	524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth	71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels	4 +
microarchitecture	Skylake (server) +
model number	D-2191 +
name	Xeon D-2191 +
number of avx-512 execution units	1 +
package	FCBGA-2518 +
part of	Edge Server and Cloud SKUs +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 2,406.00 (€ 2,165.40, £ 1,948.86, ¥ 248,611.98) +
series	D-2000 +
smp max ways	1 +
supported memory type	DDR4-2400 +
tdp	86 W (86,000 mW, 0.115 hp, 0.086 kW) +
technology	CMOS +
thread count	36 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +

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