From WikiChip
Difference between revisions of "intel/xeon d/d-2146nt"
< intel‎ | xeon d

 
(19 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon D-2146NT}}
 
{{intel title|Xeon D-2146NT}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon D-2146NT
 
|name=Xeon D-2146NT
−
|no image=Yes
+
|image=skylake-de (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=D-2146NT
 
|model number=D-2146NT
 +
|part number=FH8067303782601
 +
|s-spec=SR3ZR
 
|market=Server
 
|market=Server
 
|market 2=Embedded
 
|market 2=Embedded
 +
|first announced=February 7, 2018
 +
|first launched=February 7, 2018
 +
|release price=$641.00
 
|family=Xeon D
 
|family=Xeon D
 
|series=D-2000
 
|series=D-2000
 
|locked=Yes
 
|locked=Yes
 +
|frequency=2,300 MHz
 +
|turbo frequency1=3,000 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=23
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake (server)
 
|microarch=Skylake (server)
−
|core name=Skylake-D
+
|core name=Skylake DE
 +
|core stepping=M1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|mcp=Yes
 +
|die count=2
 
|word size=64 bit
 
|word size=64 bit
 
|core count=8
 
|core count=8
Line 23: Line 36:
 
|max cpus=1
 
|max cpus=1
 
|max memory=512 GiB
 
|max memory=512 GiB
 +
|tdp=80 W
 +
|tcase min=0 °C
 +
|tcase max=90 °C
 +
|package module 1={{packages/intel/fcbga-2518}}
 
}}
 
}}
−
'''Xeon D-2146NT''' is a {{arch|64}} [[octa-core]] high-performance [[x86]] microserver processor set to be introduced by [[Intel]] in early [[2018]]. Fabricated on Intel's [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|l=arch|Skylake microarchitecture}}, this chip operates at ? GHz with a [[TDP]] of ? W.
+
'''Xeon D-2146NT''' is a {{arch|64}} [[8-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.3 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 80 W. The D-2146NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Integrated QuickAssist Technology SKUs]].
  
  
 
{{unknown features}}
 
{{unknown features}}
 +
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=8x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=11 MiB
 +
|l3 break=8x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|ecc=Yes
 +
|max mem=512 GiB
 +
|controllers=2
 +
|channels=4
 +
|max bandwidth=79.47 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.78 GiB/s
 +
|bandwidth qchan=63.57 GiB/s
 +
|pae=46 bit
 +
}}
 +
 +
== Expansions ==
 +
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=32
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
{{expansions entry
 +
|type=HSIO
 +
|hsio lanes=20
 +
}}
 +
}}
 +
== Networking ==
 +
{{network
 +
|eth opts=Yes
 +
|10ge=Yes
 +
|10ge ports=4
 +
}}
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=1
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,300 MHz
 +
|freq_1=3,000 MHz
 +
|freq_2=3,000 MHz
 +
|freq_3=2,800 MHz
 +
|freq_4=2,800 MHz
 +
|freq_5=2,500 MHz
 +
|freq_6=2,500 MHz
 +
|freq_7=2,500 MHz
 +
|freq_8=2,500 MHz
 +
|freq_avx2_1=2,900 MHz
 +
|freq_avx2_2=2,900 MHz
 +
|freq_avx2_3=2,700 MHz
 +
|freq_avx2_4=2,700 MHz
 +
|freq_avx2_5=2,300 MHz
 +
|freq_avx2_6=2,300 MHz
 +
|freq_avx2_7=2,300 MHz
 +
|freq_avx2_8=2,300 MHz
 +
|freq_avx512_1=2,800 MHz
 +
|freq_avx512_2=2,800 MHz
 +
|freq_avx512_3=2,600 MHz
 +
|freq_avx512_4=2,600 MHz
 +
|freq_avx512_5=2,100 MHz
 +
|freq_avx512_6=2,100 MHz
 +
|freq_avx512_7=2,100 MHz
 +
|freq_avx512_8=2,100 MHz
 +
}}

Latest revision as of 23:08, 7 February 2018

Edit Values
Xeon D-2146NT
skylake-de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2146NT
Part NumberFH8067303782601
S-SpecSR3ZR
MarketServer, Embedded
IntroductionFebruary 7, 2018 (announced)
February 7, 2018 (launched)
Release Price$641.00
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency2,300 MHz
Turbo Frequency3,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier23
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake DE
Core SteppingM1
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores8
Threads16
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP80 W
Tcase0 °C – 90 °C
Packaging
PackageFCBGA-2518 (BGA)
Dimension45 mm x 52.5 mm
Contacts2518

Xeon D-2146NT is a 64-bit 8-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.3 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 80 W. The D-2146NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of Skylake DE's Integrated QuickAssist Technology SKUs.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.78 GiB/s
Quad 63.57 GiB/s
Physical Address (PAE)46 bit

Expansions[edit]

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: x16, x8, x4
HSIOMax Lanes: 20

Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 4)

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (1 Unit)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
IPTIdentity Protection Technology
QATIntegrated QuickAssist Technology

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal2,300 MHz3,000 MHz3,000 MHz2,800 MHz2,800 MHz2,500 MHz2,500 MHz2,500 MHz2,500 MHz
AVX22,900 MHz2,900 MHz2,700 MHz2,700 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz
AVX5122,800 MHz2,800 MHz2,600 MHz2,600 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-2146nt&oldid=74076"
Facts about "Xeon D-2146NT - Intel"
RDF feed
core count8 +
core nameSkylake-D +
designerIntel +
familyXeon D +
full page nameintel/xeon d/d-2146nt +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldate3000 +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
microarchitectureSkylake (server) +
model numberD-2146NT +
nameXeon D-2146NT +
process14 nm (0.014 μm, 1.4e-5 mm) +
seriesD-2000 +
smp max ways1 +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +