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Difference between revisions of "intel/xeon d/d-2191"
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{{intel title|Xeon D-2191}}
 
{{intel title|Xeon D-2191}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon D-2191
 
|name=Xeon D-2191
−
|no image=Yes
+
|image=skylake-de (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 9: Line 8:
 
|market=Server
 
|market=Server
 
|market 2=Embedded
 
|market 2=Embedded
 +
|first announced=February 7, 2018
 +
|first launched=February 7, 2018
 
|release price=$2406
 
|release price=$2406
 
|family=Xeon D
 
|family=Xeon D
Line 14: Line 15:
 
|locked=Yes
 
|locked=Yes
 
|frequency=1,600 MHz
 
|frequency=1,600 MHz
 +
|turbo frequency1=3,000 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=16
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake (server)
 
|microarch=Skylake (server)
−
|core name=Skylake-D
+
|core name=Skylake DE
 +
|core stepping=M1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|mcp=Yes
 +
|die count=2
 
|word size=64 bit
 
|word size=64 bit
 
|core count=18
 
|core count=18
Line 26: Line 35:
 
|max memory=512 GiB
 
|max memory=512 GiB
 
|tdp=86 W
 
|tdp=86 W
 +
|package module 1={{packages/intel/fcbga-2518}}
 
}}
 
}}
−
'''Xeon D-2191''' is a {{arch|64}} [[18-core]] high-performance [[x86]] microserver processor set to be introduced by [[Intel]] in early [[2018]]. Fabricated on Intel's [[14 nm process|14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|l=arch|Skylake microarchitecture}}, this chip operates at 1.6 GHz with a [[TDP]] of 86 W.
+
'''Xeon D-2191''' is a {{arch|64}} [[18-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 1.6 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 86 W. The D-2191 supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Edge Server and Cloud SKUs]].
  
  
 
{{unknown features}}
 
{{unknown features}}
 +
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=1.125 MiB
 +
|l1i cache=576 KiB
 +
|l1i break=18x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=576 KiB
 +
|l1d break=18x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=18 MiB
 +
|l2 break=18x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=24.75 MiB
 +
|l3 break=18x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=512 GiB
 +
|controllers=2
 +
|channels=4
 +
|max bandwidth=71.53 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|pae=46 bit
 +
}}
 +
 +
== Expansions ==
 +
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=32
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
{{expansions entry
 +
|type=HSIO
 +
|hsio lanes=20
 +
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=1
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=1,600 MHz
 +
|freq_1=3,000 MHz
 +
|freq_2=3,000 MHz
 +
|freq_3=2,800 MHz
 +
|freq_4=2,800 MHz
 +
|freq_5=2,700 MHz
 +
|freq_6=2,700 MHz
 +
|freq_7=2,700 MHz
 +
|freq_8=2,700 MHz
 +
|freq_9=2,500 MHz
 +
|freq_10=2,500 MHz
 +
|freq_11=2,500 MHz
 +
|freq_12=2,500 MHz
 +
|freq_13=2,300 MHz
 +
|freq_14=2,300 MHz
 +
|freq_15=2,300 MHz
 +
|freq_16=2,300 MHz
 +
|freq_17=2,200 MHz
 +
|freq_18=2,200 MHz
 +
|freq_avx2_1=2,900 MHz
 +
|freq_avx2_2=2,900 MHz
 +
|freq_avx2_3=2,700 MHz
 +
|freq_avx2_4=2,700 MHz
 +
|freq_avx2_5=2,600 MHz
 +
|freq_avx2_6=2,600 MHz
 +
|freq_avx2_7=2,600 MHz
 +
|freq_avx2_8=2,600 MHz
 +
|freq_avx2_9=2,500 MHz
 +
|freq_avx2_10=2,500 MHz
 +
|freq_avx2_11=2,500 MHz
 +
|freq_avx2_12=2,500 MHz
 +
|freq_avx2_13=2,300 MHz
 +
|freq_avx2_14=2,300 MHz
 +
|freq_avx2_15=2,300 MHz
 +
|freq_avx2_16=2,300 MHz
 +
|freq_avx2_17=2,200 MHz
 +
|freq_avx2_18=2,200 MHz
 +
|freq_avx512_1=2,800 MHz
 +
|freq_avx512_2=2,800 MHz
 +
|freq_avx512_3=2,600 MHz
 +
|freq_avx512_4=2,600 MHz
 +
|freq_avx512_5=2,300 MHz
 +
|freq_avx512_6=2,300 MHz
 +
|freq_avx512_7=2,300 MHz
 +
|freq_avx512_8=2,300 MHz
 +
|freq_avx512_9=1,900 MHz
 +
|freq_avx512_10=1,900 MHz
 +
|freq_avx512_11=1,900 MHz
 +
|freq_avx512_12=1,900 MHz
 +
|freq_avx512_13=1,700 MHz
 +
|freq_avx512_14=1,700 MHz
 +
|freq_avx512_15=1,700 MHz
 +
|freq_avx512_16=1,700 MHz
 +
|freq_avx512_17=1,700 MHz
 +
|freq_avx512_18=1,700 MHz
 +
}}

Latest revision as of 22:46, 7 February 2018

Edit Values
Xeon D-2191
skylake-de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2191
MarketServer, Embedded
IntroductionFebruary 7, 2018 (announced)
February 7, 2018 (launched)
Release Price$2406
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency1,600 MHz
Turbo Frequency3,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier16
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake DE
Core SteppingM1
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores18
Threads36
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP86 W
Packaging
PackageFCBGA-2518 (BGA)
Dimension45 mm x 52.5 mm
Contacts2518

Xeon D-2191 is a 64-bit 18-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 1.6 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 86 W. The D-2191 supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory. This model is part of Skylake DE's Edge Server and Cloud SKUs.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associative 
L1D$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associativewrite-back
L2$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  18x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels4
Max Bandwidth71.53 GiB/s
73,246.72 MiB/s
76.805 GB/s
76,804.753 MB/s
0.0699 TiB/s
0.0768 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Physical Address (PAE)46 bit

Expansions[edit]

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: x16, x8, x4
HSIOMax Lanes: 20


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (1 Unit)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
IPTIdentity Protection Technology

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718
Normal1,600 MHz3,000 MHz3,000 MHz2,800 MHz2,800 MHz2,700 MHz2,700 MHz2,700 MHz2,700 MHz2,500 MHz2,500 MHz2,500 MHz2,500 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz2,200 MHz2,200 MHz
AVX22,900 MHz2,900 MHz2,700 MHz2,700 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,500 MHz2,500 MHz2,500 MHz2,500 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz2,200 MHz2,200 MHz
AVX5122,800 MHz2,800 MHz2,600 MHz2,600 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz1,900 MHz1,900 MHz1,900 MHz1,900 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-2191&oldid=74055"
Facts about "Xeon D-2191 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-2191 - Intel#package + and Xeon D-2191 - Intel#pcie +
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier16 +
core count18 +
core nameSkylake DE +
core steppingM1 +
designerIntel +
die count2 +
familyXeon D +
first announcedFebruary 7, 2018 +
first launchedFebruary 7, 2018 +
full page nameintel/xeon d/d-2191 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description16-way set associative +
l2$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateFebruary 7, 2018 +
main imageFile:skylake-de (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max hsio lanes20 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) +
max memory channels4 +
microarchitectureSkylake (server) +
model numberD-2191 +
nameXeon D-2191 +
number of avx-512 execution units1 +
packageFCBGA-2518 +
part ofEdge Server and Cloud SKUs +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,406.00 (€ 2,165.40, £ 1,948.86, ¥ 248,611.98) +
seriesD-2000 +
smp max ways1 +
supported memory typeDDR4-2400 +
tdp86 W (86,000 mW, 0.115 hp, 0.086 kW) +
technologyCMOS +
thread count36 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +