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{{intel title|Xeon D-2161I}} | {{intel title|Xeon D-2161I}} | ||
− | {{chip}}} | + | {{chip |
+ | |name=Xeon D-2161I | ||
+ | |image=skylake-de (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=D-2161I | ||
+ | |part number=FH8067303534104 | ||
+ | |s-spec=SR3ZN | ||
+ | |market=Server | ||
+ | |market 2=Embedded | ||
+ | |first announced=February 7, 2018 | ||
+ | |first launched=February 7, 2018 | ||
+ | |release price=$962.00 | ||
+ | |family=Xeon D | ||
+ | |series=D-2000 | ||
+ | |locked=Yes | ||
+ | |frequency=2,200 MHz | ||
+ | |turbo frequency1=3,000 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=22 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |core name=Skylake DE | ||
+ | |core stepping=M1 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |mcp=Yes | ||
+ | |die count=2 | ||
+ | |word size=64 bit | ||
+ | |core count=12 | ||
+ | |thread count=24 | ||
+ | |max cpus=1 | ||
+ | |max memory=512 GiB | ||
+ | |tdp=90 W | ||
+ | |package module 1={{packages/intel/fcbga-2518}} | ||
+ | }} | ||
+ | '''Xeon D-2161I''' is a {{arch|64}} [[12-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.2 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 90 W. The D-2161I supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Edge Server and Cloud SKUs]]. | ||
+ | |||
+ | |||
+ | {{unknown features}} | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=12 MiB | ||
+ | |l2 break=12x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=16.5 MiB | ||
+ | |l3 break=12x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2133 | ||
+ | |ecc=Yes | ||
+ | |max mem=512 GiB | ||
+ | |controllers=2 | ||
+ | |channels=4 | ||
+ | |max bandwidth=79.47 GiB/s | ||
+ | |bandwidth schan=15.89 GiB/s | ||
+ | |bandwidth dchan=31.78 GiB/s | ||
+ | |bandwidth qchan=63.57 GiB/s | ||
+ | |pae=46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports. | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=32 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=HSIO | ||
+ | |hsio lanes=20 | ||
+ | }} | ||
+ | }} | ||
+ | == Networking == | ||
+ | {{network | ||
+ | |eth opts=Yes | ||
+ | |10ge=Yes | ||
+ | |10ge ports=4 | ||
+ | }} | ||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512units=1 | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,200 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,800 MHz | ||
+ | |freq_4=2,800 MHz | ||
+ | |freq_5=2,800 MHz | ||
+ | |freq_6=2,800 MHz | ||
+ | |freq_7=2,800 MHz | ||
+ | |freq_8=2,800 MHz | ||
+ | |freq_9=2,800 MHz | ||
+ | |freq_10=2,800 MHz | ||
+ | |freq_11=2,800 MHz | ||
+ | |freq_12=2,800 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,700 MHz | ||
+ | |freq_avx2_4=2,700 MHz | ||
+ | |freq_avx2_5=2,700 MHz | ||
+ | |freq_avx2_6=2,700 MHz | ||
+ | |freq_avx2_7=2,700 MHz | ||
+ | |freq_avx2_8=2,700 MHz | ||
+ | |freq_avx2_9=2,700 MHz | ||
+ | |freq_avx2_10=2,700 MHz | ||
+ | |freq_avx2_11=2,700 MHz | ||
+ | |freq_avx2_12=2,700 MHz | ||
+ | |freq_avx512_1=2,800 MHz | ||
+ | |freq_avx512_2=2,800 MHz | ||
+ | |freq_avx512_3=2,600 MHz | ||
+ | |freq_avx512_4=2,600 MHz | ||
+ | |freq_avx512_5=2,500 MHz | ||
+ | |freq_avx512_6=2,500 MHz | ||
+ | |freq_avx512_7=2,500 MHz | ||
+ | |freq_avx512_8=2,500 MHz | ||
+ | |freq_avx512_9=2,200 MHz | ||
+ | |freq_avx512_10=2,200 MHz | ||
+ | |freq_avx512_11=2,200 MHz | ||
+ | |freq_avx512_12=2,200 MHz | ||
+ | }} |
Latest revision as of 23:59, 7 February 2018
Edit Values | |||||||
Xeon D-2161I | |||||||
![]() | |||||||
General Info | |||||||
Designer | Intel | ||||||
Manufacturer | Intel | ||||||
Model Number | D-2161I | ||||||
Part Number | FH8067303534104 | ||||||
S-Spec | SR3ZN | ||||||
Market | Server, Embedded | ||||||
Introduction | February 7, 2018 (announced) February 7, 2018 (launched) | ||||||
Release Price | $962.00 | ||||||
Shop | Amazon | ||||||
General Specs | |||||||
Family | Xeon D | ||||||
Series | D-2000 | ||||||
Locked | Yes | ||||||
Frequency | 2,200 MHz | ||||||
Turbo Frequency | 3,000 MHz (1 core) | ||||||
Bus type | DMI 3.0 | ||||||
Bus rate | 4 × 8 GT/s | ||||||
Clock multiplier | 22 | ||||||
Microarchitecture | |||||||
ISA | x86-64 (x86) | ||||||
Microarchitecture | Skylake (server) | ||||||
Core Name | Skylake DE | ||||||
Core Stepping | M1 | ||||||
Process | 14 nm | ||||||
Technology | CMOS | ||||||
MCP | Yes (2 dies) | ||||||
Word Size | 64 bit | ||||||
Cores | 12 | ||||||
Threads | 24 | ||||||
Max Memory | 512 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
TDP | 90 W | ||||||
Packaging | |||||||
|
Xeon D-2161I is a 64-bit 12-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.2 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 90 W. The D-2161I supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of Skylake DE's Edge Server and Cloud SKUs.
Cache[edit]
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
![]() |
Expansion Options |
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Networking[edit]
![]() |
Networking
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,200 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz |
AVX2 | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | |
AVX512 | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,500 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz |
Facts about "Xeon D-2161I - Intel"
full page name | intel/xeon d/d-2161i + |
instance of | microprocessor + |
ldate | 1900 + |