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Difference between revisions of "intel/core i3/i3-8121u"
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{{intel title|Core i3-8121U}}
 
{{intel title|Core i3-8121U}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Core i3-8121U
 
|name=Core i3-8121U
 
|no image=Yes
 
|no image=Yes
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|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=i3-8121U
 
|model number=i3-8121U
 +
|s-spec=SRCVC
 
|market=Mobile
 
|market=Mobile
 +
|first announced=May 15, 2018
 +
|first launched=May 15, 2018
 
|family=Core i3
 
|family=Core i3
 
|series=i3-8000
 
|series=i3-8000
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,200 MHz
 
|frequency=2,200 MHz
 +
|turbo frequency1=3,200 MHz
 
|bus type=OPI
 
|bus type=OPI
 
|bus rate=4 GT/s
 
|bus rate=4 GT/s
 
|clock multiplier=22
 
|clock multiplier=22
 +
|cpuid=60663
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Cannon Lake
 
|microarch=Cannon Lake
 
|core name=Cannon Lake U
 
|core name=Cannon Lake U
 +
|core family=6
 +
|core model=102
 
|process=10 nm
 
|process=10 nm
 
|technology=CMOS
 
|technology=CMOS
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|thread count=4
 
|thread count=4
 
|max cpus=1
 
|max cpus=1
 +
|max memory=32 GiB
 
|tdp=15 W
 
|tdp=15 W
 +
|tjunc min=0 °C
 +
|tjunc max=105 °C
 
|tstorage min=-25 °C
 
|tstorage min=-25 °C
 
|tstorage max=125 °C
 
|tstorage max=125 °C
−
|package module 1={{packages/intel/fcbga-1356}}
 
 
}}
 
}}
−
'''Core i3-8121U''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in early 2018. This chip, which is based on the {{intel|Cannon Lake|l=arch}} microarchitecture, is fabricated on Intel's [[10 nm process]]. This processor, which has a base frequency of 2.2 GHz with a TDP of 15 Watts, supports up to 32 GiB of dual-channel DDR4-2400. <!--The i3-8121U incorporates Intel's {{intel|HD Graphics 720}} [[IGP]] operating at 300 MHz with burst frequency of 1 GHz.-->
+
'''Core i3-8121U''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] mobile microprocessor introduced by [[Intel]] in early 2018. This chip is fabricated on Intel's [[10 nm process]] and is based on the {{intel|Cannon Lake|l=arch}} microarchitecture. The i3-8121U has a base frequency of 2.2 GHz with a TDP of 15 Watts and a {{intel|turbo boost}} of 3.2 GHz. This chip supports up to 32 GiB of dual-channel DDR4/LPDDR4X-2400 memory and has no integrated graphics processor.
  
  
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type 3=DDR4-2400
+
|type=DDR4-2400
 +
|type 2=LPDDR4-2400
 +
|type 3=LPDDR4X-2400
 
|ecc=No
 
|ecc=No
 
|controllers=1
 
|controllers=1
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|bandwidth dchan=35.76 GiB/s
 
|bandwidth dchan=35.76 GiB/s
 
}}
 
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=16
 +
|pcie config=1x4
 +
|pcie config 2=2x2
 +
|pcie config 3=1x2+2x1
 +
|pcie config 4=4x1
 +
}}
 +
}}
 +
 +
== Graphics ==
 +
This chip has no integrated graphics processor.
  
 
== Features ==
 
== Features ==
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
 
+
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=Yes
 +
|avx512vbmi=Yes
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
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|aes=Yes
 
|aes=Yes
 
|rdrand=Yes
 
|rdrand=Yes
−
|sha=No
+
|sha=Yes
 
|xop=No
 
|xop=No
 
|adx=Yes
 
|adx=Yes
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|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
−
|tbt2=No
+
|tbt2=Yes
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
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|flex=Yes
 
|flex=Yes
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 
|isrt=Yes
 
|isrt=Yes
 
|sba=No
 
|sba=No
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|securekey=Yes
 
|securekey=Yes
 
|osguard=Yes
 
|osguard=Yes
 +
|intqat=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
 
|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}

Latest revision as of 16:43, 22 June 2018

Edit Values
Core i3-8121U
General Info
DesignerIntel
ManufacturerIntel
Model Numberi3-8121U
S-SpecSRCVC
MarketMobile
IntroductionMay 15, 2018 (announced)
May 15, 2018 (launched)
ShopAmazon
General Specs
FamilyCore i3
Seriesi3-8000
LockedYes
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core)
Bus typeOPI
Bus rate4 GT/s
Clock multiplier22
CPUID60663
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCannon Lake
Core NameCannon Lake U
Core Family6
Core Model102
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads4
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP15 W
Tjunction0 °C – 105 °C
Tstorage-25 °C – 125 °C

Core i3-8121U is a 64-bit dual-core low-end performance x86 mobile microprocessor introduced by Intel in early 2018. This chip is fabricated on Intel's 10 nm process and is based on the Cannon Lake microarchitecture. The i3-8121U has a base frequency of 2.2 GHz with a TDP of 15 Watts and a turbo boost of 3.2 GHz. This chip supports up to 32 GiB of dual-channel DDR4/LPDDR4X-2400 memory and has no integrated graphics processor.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Cannon Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400, LPDDR4-2400, LPDDR4X-2400
Supports ECCNo
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 1x4, 2x2, 1x2+2x1, 4x1


Graphics[edit]

This chip has no integrated graphics processor.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_IFMAAVX-512 Integer Fused Multiply-Add
AVX512_VBMIAVX-512 Vector Bit Manipulation Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-8121u&oldid=79475"
Facts about "Core i3-8121U - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i3-8121U - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus typeOPI +
clock multiplier22 +
core count2 +
core family6 +
core model102 +
core nameCannon Lake U +
cpuid60663 +
designerIntel +
familyCore i3 +
first announcedMay 15, 2018 +
first launchedMay 15, 2018 +
full page nameintel/core i3/i3-8121u +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel identity protection technology supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description16-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateMay 15, 2018 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureCannon Lake +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberi3-8121U +
nameCore i3-8121U +
process10 nm (0.01 μm, 1.0e-5 mm) +
s-specSRCVC +
seriesi3-8000 +
smp max ways1 +
supported memory typeDDR4-2400 +, LPDDR4-2400 + and LPDDR4X-2400 +
tdp15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +