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Difference between revisions of "intel/microarchitectures/goldmont plus"
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|extension 11=PCLMUL
 
|extension 11=PCLMUL
 
|extension 12=RDRND
 
|extension 12=RDRND
−
|extension 13=SHA
+
|extension 13=XSAVE
 +
|extension 14=XSAVEOPT
 +
|extension 15=FSGSBASE
 +
|extension 16=PTWRITE
 +
|extension 17=RDPID
 +
|extension 18=SGX
 +
|extension 19=UMIP
 +
|extension 20=SHA
 
|l1i=32 KiB
 
|l1i=32 KiB
 
|l1i per=Core
 
|l1i per=Core
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|l1d per=Core
 
|l1d per=Core
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
−
|l2=2 MiB
+
|l2=4 MiB
−
|l2 per=2 Cores
+
|l2 per=4 Cores
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|core name=Gemini Lake
 
|core name=Gemini Lake
 +
|core name 2=Gemini Lake Refresh
 
|predecessor=Goldmont
 
|predecessor=Goldmont
 
|predecessor link=intel/microarchitectures/goldmont
 
|predecessor link=intel/microarchitectures/goldmont
 +
|successor=Tremont
 +
|successor link=intel/microarchitectures/tremont
 
}}
 
}}
−
'''Goldmont Plus''' ('''GLM+''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium Silver}}, and {{intel|Celeron}} families.
+
'''Goldmont Plus''' ('''GLM+''', '''GLP''') is [[Intel]]'s [[14 nm]] [[microarchitecture]] of [[system on chip]]s for the ultra-low power (ULP) devices serving as a successor to {{\\|Goldmont}}. Goldmont Plus-based processors and SoCs are part of the {{intel|Atom}}, {{intel|Pentium Silver}}, and {{intel|Celeron}} families.
  
 
== Codenames ==
 
== Codenames ==
Line 48: Line 58:
 
|-
 
|-
 
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices
 
| {{intel|Gemini Lake}} || GLK || Low-power PCs, tablets, and embedded devices
 +
|-
 +
| {{intel|Gemini Lake Refresh}} || GLK || Low-power PCs, tablets, and embedded devices
 
|}
 
|}
  
Line 65: Line 77:
  
 
== Release Dates ==
 
== Release Dates ==
−
Goldmont Plus processors were launched on December 11 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.
+
Goldmont Plus processors were launched on December 11, 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.
  
 
== Technology ==
 
== Technology ==
−
Goldmont Plus, like its predecessor is manufactured on Intel's original [[14 nm process]] (as opposed to 14nm+ or 14nm++).
+
Goldmont Plus, like its predecessor, is manufactured on Intel's original [[14 nm process]] (as opposed to 14nm+ or 14nm++).
  
 
== Compiler support ==
 
== Compiler support ==
Line 89: Line 101:
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
−
| rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || ? || ? || ?
+
| rowspan="2" | {{intel|Gemini Lake|l=core}} || 0 || 0x6 || 0x7 || 0xA
 
|-
 
|-
−
| colspan="4" | Family 6 Model ?
+
| colspan="4" | Family 6 Model 122
 
|}
 
|}
  
 
== Architecture ==
 
== Architecture ==
−
{{future information}}
+
Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.
 
=== Key changes from {{\\|Goldmont}} ===
 
=== Key changes from {{\\|Goldmont}} ===
 +
* Core
 +
** Front End
 +
*** Enhanced branch prediction
 +
** Back End
 +
*** 4-way allocation (from 3)
 +
*** 4-way retire (from 3)
 +
** Larger reservation station
 +
** Larger ROB
 +
** Execution Units
 +
*** POPF latency reduced from ~80 to ~40 cycles
 +
*** Vector divisions and square roots are faster
 +
*** AES operations: latency reduced from 6 to 4 cycles, throughput increased to 1 op/cycle
 +
*** SHL, SHR, SAR, ROL and ROR with counter in CL: latency reduced from 2 to 1
 +
** Wider integer execution unit
 +
** New dedicated JEU port
 +
*** Supports faster branch redirection.
 +
** Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides
 +
** Improved {{x86|AES}} instruction latency and throughput.
 +
** Memory Subsystem
 +
*** 64 KiB 2nd level pre-decode cache (from 16 KiB)
 +
*** Larger load buffer
 +
*** Larger store buffer
 +
*** Improved store-to-load forwarding latency store data from register
 +
*** New STLB
 +
**** Shared by instruction and data
 +
*** Paging Cache Enhancements (PxE/ePxE caches)
 +
* Cache
 +
** 4 MiB L2 per quad core module (Up from 1 MiB per duplex)
 +
* Graphics
 +
** {{intel|Gen 9.5|l=arch}} execution engines, {{intel|Gen 10|l=arch}} Display
 
* New Integration
 
* New Integration
 
** {{intel|CNVi|Integrated Connectivity CNVi}}
 
** {{intel|CNVi|Integrated Connectivity CNVi}}
 
*** Supports up to Wireless-AC CRFs
 
*** Supports up to Wireless-AC CRFs
−
* Cache
 
−
** 2 MiB L2 per duplex (Up from 1 MiB)
 
−
* Graphics
 
−
** {{intel|Gen 9.5|l=arch}} execution engines, {{intel|Gen 10|l=arch}} Display
 
 
** HDMI 2.0 (from 1.4a)
 
** HDMI 2.0 (from 1.4a)
 
*** 2160p (4K) @ 60 Hz (from 24 Hz)
 
*** 2160p (4K) @ 60 Hz (from 24 Hz)
Line 131: Line 169:
 
*** 2 MiB 16-way set associative, 64 B line size
 
*** 2 MiB 16-way set associative, 64 B line size
 
*** Per 2 cores
 
*** Per 2 cores
 +
*** 32B/cycle, 19 cycle latency
 
** L3 Cache:
 
** L3 Cache:
 
*** No level 3 cache
 
*** No level 3 cache

Latest revision as of 12:28, 17 July 2023

Edit Values
Goldmont Plus µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionDecember 11, 2017
Process14 nm
Core Configs2, 4
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, SHA
Cache
L1I Cache32 KiB/Core
8-way set associative
L1D Cache24 KiB/Core
6-way set associative
L2 Cache4 MiB/4 Cores
16-way set associative
Cores
Core NamesGemini Lake,
Gemini Lake Refresh
Succession

Goldmont Plus (GLM+, GLP) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium Silver, and Celeron families.

Codenames[edit]

Core Abbrev Target
Gemini Lake GLK Low-power PCs, tablets, and embedded devices
Gemini Lake Refresh GLK Low-power PCs, tablets, and embedded devices

Brands[edit]

Intel released Goldmont Plus under 2 main brand families:

Logo Family General Description Differentiating Features
Cores HT AES SHA AVX TBT ECC
intel celeron (2015).png Celeron Entry-level Budget 2-4 ✘ ✔ ✔ ✘ ✘ ✘
intel pentium silver logo (2017).png Pentium Silver Budget 4 ✘ ✔ ✔ ✘ ✘ ✘

Release Dates[edit]

Goldmont Plus processors were launched on December 11, 2017 for desktop, mobile and embedded devices. Server-based parts are expected to be introduced in 2018.

Technology[edit]

Goldmont Plus, like its predecessor, is manufactured on Intel's original 14 nm process (as opposed to 14nm+ or 14nm++).

Compiler support[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Compiler Arch-Specific Arch-Favorable
ICC -march=goldmont -mtune=goldmont
GCC -march=goldmont -mtune=goldmont
LLVM -march=goldmont -mtune=goldmont
Visual Studio ? ?

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
Gemini Lake 0 0x6 0x7 0xA
Family 6 Model 122

Architecture[edit]

Despite the name "Goldmont Plus", this microarchitecture is a very large implementational jump from "Goldmont" with improvements across the board from the caches to a wider pipeline.

Key changes from Goldmont[edit]

  • Core
    • Front End
      • Enhanced branch prediction
    • Back End
      • 4-way allocation (from 3)
      • 4-way retire (from 3)
    • Larger reservation station
    • Larger ROB
    • Execution Units
      • POPF latency reduced from ~80 to ~40 cycles
      • Vector divisions and square roots are faster
      • AES operations: latency reduced from 6 to 4 cycles, throughput increased to 1 op/cycle
      • SHL, SHR, SAR, ROL and ROR with counter in CL: latency reduced from 2 to 1
    • Wider integer execution unit
    • New dedicated JEU port
      • Supports faster branch redirection.
    • Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides
    • Improved AES instruction latency and throughput.
    • Memory Subsystem
      • 64 KiB 2nd level pre-decode cache (from 16 KiB)
      • Larger load buffer
      • Larger store buffer
      • Improved store-to-load forwarding latency store data from register
      • New STLB
        • Shared by instruction and data
      • Paging Cache Enhancements (PxE/ePxE caches)
  • Cache
    • 4 MiB L2 per quad core module (Up from 1 MiB per duplex)
  • Graphics
  • New Integration

New instructions[edit]

Goldmont Plus introduced a number of new instructions:

  • SGX1 - Software Guard Extensions, Version 1
  • UMIP - User-mode instruction prevention
  • PTWRITE - Trace logger write user data
  • RDPID - Read Processor ID

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KiB 8-way set associative instruction, 64 B line size
      • 24 KiB 6-way set associative data, 64 B line size
      • Per core
    • L2 Cache:
      • 2 MiB 16-way set associative, 64 B line size
      • Per 2 cores
      • 32B/cycle, 19 cycle latency
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
      • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading[edit]

Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.

New Integration[edit]

Integrated Connectivity (CNVi)[edit]

Main article: CNVi

A new integration to Goldmont Plus is Integrated Connectivity (CNVi) which is an architecture for wireless connectivity devices. CNVi attempts to simplify vendors bill of material (BOM) size and cost by integrating the majority of the expensive functionality found in an RF chip. The only thing not integrated are the actual analog and RF functions which come from a relatively inexpensive companion RF (CRF) module connected via a standard M.2 card and provides support for things such as IEEE 802.11ac.

All Goldmont Plus Chips[edit]

 List of Goldmont Plus-based Processors
 Main processorGPU
ModelFamilyPriceLaunchedCoresL2$TDPSDPBaseTurboNameBaseTurbo
 Desktop
J4005Celeron$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
11 December 201724 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
10 W
10,000 mW
0.0134 hp
0.01 kW
2,000 MHz
2 GHz
2,000,000 kHz
2,700 MHz
2.7 GHz
2,700,000 kHz
UHD Graphics 600250 MHz
0.25 GHz
250,000 KHz
700 MHz
0.7 GHz
700,000 KHz
J4105Celeron$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
11 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
10 W
10,000 mW
0.0134 hp
0.01 kW
1,500 MHz
1.5 GHz
1,500,000 kHz
2,500 MHz
2.5 GHz
2,500,000 kHz
UHD Graphics 600250 MHz
0.25 GHz
250,000 KHz
750 MHz
0.75 GHz
750,000 KHz
J5005Pentium Silver$ 161.00
€ 144.90
£ 130.41
¥ 16,636.13
11 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
10 W
10,000 mW
0.0134 hp
0.01 kW
1,500 MHz
1.5 GHz
1,500,000 kHz
2,800 MHz
2.8 GHz
2,800,000 kHz
UHD Graphics 605250 MHz
0.25 GHz
250,000 KHz
800 MHz
0.8 GHz
800,000 KHz
 Mobile
N4000Celeron$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
11 December 201724 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
6 W
6,000 mW
0.00805 hp
0.006 kW
4.8 W
4,800 mW
0.00644 hp
0.0048 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
2,600 MHz
2.6 GHz
2,600,000 kHz
UHD Graphics 600200 MHz
0.2 GHz
200,000 KHz
650 MHz
0.65 GHz
650,000 KHz
N4100Celeron$ 107.00
€ 96.30
£ 86.67
¥ 11,056.31
11 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
6 W
6,000 mW
0.00805 hp
0.006 kW
4.8 W
4,800 mW
0.00644 hp
0.0048 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
2,400 MHz
2.4 GHz
2,400,000 kHz
UHD Graphics 600200 MHz
0.2 GHz
200,000 KHz
700 MHz
0.7 GHz
700,000 KHz
N5000Pentium Silver$ 161.00
€ 144.90
£ 130.41
¥ 16,636.13
11 December 201744 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
6 W
6,000 mW
0.00805 hp
0.006 kW
4.8 W
4,800 mW
0.00644 hp
0.0048 kW
1,100 MHz
1.1 GHz
1,100,000 kHz
2,700 MHz
2.7 GHz
2,700,000 kHz
UHD Graphics 605200 MHz
0.2 GHz
200,000 KHz
750 MHz
0.75 GHz
750,000 KHz
Count: 6
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/goldmont_plus&oldid=101852"
Facts about "Goldmont Plus - Microarchitectures - Intel"
RDF feed
codenameGoldmont Plus +
core count2 + and 4 +
designerIntel +
first launchedDecember 11, 2017 +
full page nameintel/microarchitectures/goldmont plus +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGoldmont Plus +
process14 nm (0.014 μm, 1.4e-5 mm) +