Difference between revisions of "intel/xeon gold/6132"

	Edit Values
	Xeon Gold 6132
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6132
Part Number	CD8067303592500
S-Spec	SR3J3; QN33 (QS)
Market	Server
Introduction	April 25, 2017 (announced); July 11, 2017 (launched)
Release Price	$2111.00
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6100
Locked	Yes
Frequency	2,600 MHz
Turbo Frequency	3,700 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	26
CPUID	0x50654
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	14
Threads	28
Max Memory	768 GiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
	Electrical
TDP	140 W
Tcase	0 °C – 86 °C
TDTS	0 °C – 101 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Latest revision as of 00:20, 29 December 2019

Xeon Gold 6132 is a 64-bit tetradeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6132, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 140 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

896 KiB

917,504 B
0.875 MiB

L1I$	448 KiB 458,752 B 0.438 MiB	14x32 KiB	8-way set associative
L1D$	448 KiB 458,752 B 0.438 MiB	14x32 KiB	8-way set associative	write-back

L2$

14 MiB

14,336 KiB
14,680,064 B
0.0137 GiB

		14x1 MiB	16-way set associative	write-back

L3$

19.25 MiB

19,712 KiB
20,185,088 B
0.0188 GiB

		14x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
Run Sure	Run Sure Technology (RAS Capability)
MBE Ctrl	Mode-Based Execute Control
Node Ctrlr	Node Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10	11	12	13	14
Normal	2,600 MHz	3,700 MHz	3,700 MHz	3,500 MHz	3,500 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz
AVX2	2,200 MHz	3,600 MHz	3,600 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,000 MHz	3,000 MHz	3,000 MHz	3,000 MHz	2,900 MHz	2,900 MHz
AVX512	1,700 MHz	3,500 MHz	3,500 MHz	3,300 MHz	3,300 MHz	2,800 MHz	2,800 MHz	2,800 MHz	2,800 MHz	2,400 MHz	2,400 MHz	2,400 MHz	2,400 MHz	2,300 MHz	2,300 MHz

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-10-23 22:16:52-0400
Chips: 2, Cores: 28, Copies: 56

Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)

SPECrate2017_int_base: 162

SPECrate2017_int_peak: 171

Test: SPEC CPU2017
Tested: 2017-10-24 01:17:47-0400
Chips: 2, Cores: 28, Threads: 28

Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)

SPECspeed2017_int_base: 8.71

SPECspeed2017_int_peak: 8.97

Test: SPEC CPU2017
Tested: 2017-10-24 06:23:50-0400
Chips: 2, Cores: 28, Threads: 28

Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)

SPECspeed2017_fp_base: 103

SPECspeed2017_fp_peak: 104

Test: SPEC CPU2017
Tested: 2017-10-23 05:14:22-0400
Chips: 2, Cores: 28, Copies: 56

Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)

SPECrate2017_fp_base: 163

SPECrate2017_fp_peak: 167

@@ Line 1: / Line 1: @@
 {{intel title|Xeon Gold 6132}}
-{{mpu
+{{chip
 |name=Xeon Gold 6132
 |image=skylake sp (basic).png
@@ Line 14: / Line 14: @@
 |release price=$2111.00
 |family=Xeon Gold
-|series=6000
+|series=6100
 |locked=Yes
 |frequency=2,600 MHz
@@ Line 35: / Line 35: @@
 |word size=64 bit
 |core count=14
-|thread count=24
+|thread count=28
+|max memory=768 GiB
 |max cpus=4
-|max memory=768 GiB
+|smp interconnect=UPI
+|smp interconnect links=3
+|smp interconnect rate=10.4 GT/s
 |tdp=140 W
 |tcase min=0 °C
@@ Line 43: / Line 46: @@
 |dts min=0 °C
 |dts max=101 °C
-|package module 1={{packages/intel/fclga-3647}}
+|package name 1=intel,fclga_3647
 }}
 '''Xeon Gold 6132''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6132, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 140 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
@@ Line 237: / Line 240: @@
 {{benchmarks main
 |
-{{benchmark entry
+{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00371.html|test_timestamp=2017-10-23 22:16:52-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECrate2017_int_base=162|SPECrate2017_int_peak=171}}
-|type=spec
+{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00373.html|test_timestamp=2017-10-24 01:17:47-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECspeed2017_int_base=8.71|SPECspeed2017_int_peak=8.97}}
-|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00401.html
+{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00377.html|test_timestamp=2017-10-24 06:23:50-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECspeed2017_fp_base=103|SPECspeed2017_fp_peak=104}}
-|test_timestamp=2017-10-23 05:14:22-0400
+{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00401.html|test_timestamp=2017-10-23 05:14:22-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECrate2017_fp_base=163|SPECrate2017_fp_peak=167}}
-|chip_count=2
-|core_count=28
-|copies_count=56
-|vendor=Cisco Systems
-|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
-|SPECrate2017_fp_base=163
-|SPECrate2017_fp_peak=167
-}}
 }}
 [[Category:microprocessor models by intel based on skylake extreme core count die]]

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6132 - Intel#io +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
l1$ size	896 KiB (917,504 B, 0.875 MiB) +
l1d$ description	8-way set associative +
l1d$ size	448 KiB (458,752 B, 0.438 MiB) +
l1i$ description	8-way set associative +
l1i$ size	448 KiB (458,752 B, 0.438 MiB) +
l2$ description	16-way set associative +
l2$ size	14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) +
l3$ description	11-way set associative +
l3$ size	19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
supported memory type	DDR4-2666 +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Latest revision as of 00:20, 29 December 2019

Contents

Cache[edit]

Memory controller[edit]

Expansions[edit]

Features[edit]

Frequencies[edit]

Benchmarks[edit]