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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
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{{pezy title|PEZY-SCnp}}
 
{{pezy title|PEZY-SCnp}}
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{{mpu
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{{chip
 
|name=PEZY-SCnp
 
|name=PEZY-SCnp
 
|image=pezy-scnp (front).png
 
|image=pezy-scnp (front).png
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|process=28 nm
 
|process=28 nm
 
|technology=CMOS
 
|technology=CMOS
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|die area=411.6 mm²
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|core count=1,024
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|die length=19.5 mm
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|thread count=8,192
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|die width=21.1 mm
 
−
|core count=1024
 
 
|power=100 W
 
|power=100 W
 
|average power=70 W
 
|average power=70 W
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|socket 0 type=BGA
 
|socket 0 type=BGA
 
}}
 
}}
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'''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]).
+
'''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 [[TFLOPS]] (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on [[28 nm process|TSMC's 28HPC+]].
 +
{{#set:
 +
| peak flops (single-precision) = {{#expr:766666666 * 4 * 1024}} FLOPS
 +
| peak flops (double-precision) = {{#expr:766666666 * 2 * 1024}} FLOPS
 +
}}
  
 
== Architecture ==
 
== Architecture ==
−
{{main|pezy/pezy-sc#Architecture|l1=PEZY-SC §Architecture}}
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{{further|pezy/pezy-scx/pezy-sc#Architecture|pezy/pezy-scx#Architecture|l1=PEZY-SC § Architecture|l2=PEZY-SCx § Architecture}}
 
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
 
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
  
 
== Cache ==
 
== Cache ==
 
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
 
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
 +
{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=2x16 KiB
 +
|l1d cache=32 KiB
 +
|l1d break=2x16 KiB
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
}}
 +
 +
The chip integrates a multi-level cache hierarchy:
 
{{cache size
 
{{cache size
 
|l1 cache=3 MiB
 
|l1 cache=3 MiB
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|l3 policy=
 
|l3 policy=
 
}}
 
}}
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 +
Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.
  
 
== Memory controller ==
 
== Memory controller ==

Latest revision as of 10:15, 22 September 2018

Edit Values
PEZY-SCnp
pezy-scnp (front).png
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SCnp
MarketSupercomputer
IntroductionMay 6, 2016 (announced)
May 6, 2016 (launched)
General Specs
FamilyPEZY-SCx
Frequency766.66 MHz
Microarchitecture
Process28 nm
TechnologyCMOS
Cores1,024
Threads8,192
Electrical
Power dissipation100 W
Power dissipation (average)70 W
Vcore0.95 V
Packaging
PackageFCBGA-2397 (BGA)pezy-scnp (back).png
Dimension50 mm x 50 mm
Pitch1 mm
Contacts2,397

PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 TFLOPS (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+.


Architecture[edit]

Further information: PEZY-SC § Architecture and PEZY-SCx § Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache[edit]

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
2x16 KiB  
L1D$32 KiB
32,768 B
0.0313 MiB
2x16 KiB  
L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB  

The chip integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
L1I$2 MiB
2,048 KiB
2,097,152 B
1024x2 KiBper processor element 
L1D$1 MiB
1,024 KiB
1,048,576 B
512x2 KiBper 2 processor elements 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x2 MiBper citywrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiBper prefecture 

Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Controllers8
Channels8
Width64 bit
Max Bandwidth127.156 GiB/s
130,207.744 MiB/s
136.533 GB/s
136,532.715 MB/s
0.124 TiB/s
0.137 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/
Hexa 95.37 GiB/s
Octa 127.156 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: 4x8
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Facts about "PEZY-SCnp - PEZY"
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PEZY-SCnp - PEZY#pcie +
has ecc memory supporttrue +
l1$ size3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ descriptionper processor element +
l1i$ size2,048 KiB (2,097,152 B, 2 MiB) +
l2$ descriptionper city +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
supported memory typeDDR4-2133 +