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PEZY-SCnp - PEZY
< pezy‎ | pezy-scx

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PEZY-SCnp
pezy-scnp (front).png
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SCnp
MarketSupercomputer
IntroductionMay 6, 2016 (announced)
May 6, 2016 (launched)
General Specs
FamilyPEZY-SCx
Frequency766.66 MHz
Microarchitecture
Process28 nm
TechnologyCMOS
Cores1,024
Threads8,192
Electrical
Power dissipation100 W
power dissipation (average)70 W
Vcore0.95 V
Packaging
PackageFCBGA-2397 (BGA)pezy-scnp (back).png
Dimension50 mm x 50 mm
Pitch1 mm
Contacts2,397

PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 TFLOPS (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+.


Architecture[edit]

Further information: PEZY-SC § Architecture and PEZY-SCx § Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache[edit]

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
L1I$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
2x16 KiB  
L1D$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
2x16 KiB  

L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB  

The chip integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
L1I$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
1024x2 KiBper processor element 
L1D$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
512x2 KiBper 2 processor elements 

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x2 MiBper citywrite-back

L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiBper prefecture 

Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Controllers8
Channels8
Width64 bit
Max Bandwidth127.156 GiB/s
221.251 GB/s
130,207.744 MiB/s
0.124 TiB/s
0.137 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/
Hexa 95.37 GiB/s
Octa 127.156 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: 4x8
Facts about "PEZY-SCnp - PEZY"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-SCnp - PEZY#package + and PEZY-SCnp - PEZY#pcie +
base frequency766.66 MHz (0.767 GHz, 766,660 kHz) +
core count1,024 +
core voltage0.95 V (9.5 dV, 95 cV, 950 mV) +
designerPEZY +
familyPEZY-SCx +
first announcedMay 6, 2016 +
first launchedMay 6, 2016 +
full page namepezy/pezy-scx/pezy-scnp +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + and 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l1i$ descriptionper processor element +
l1i$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + and 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l2$ descriptionper city +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateMay 6, 2016 +
main imageFile:pezy-scnp (front).png +
manufacturerTSMC +
market segmentSupercomputer +
max memory bandwidth127.156 GiB/s (221.251 GB/s, 130,207.744 MiB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
model numberPEZY-SCnp +
namePEZY-SCnp +
packageFCBGA-2397 +
peak flops (double-precision)1,570,133,331,968 FLOPS (1,570,133,331.968 KFLOPS, 1,570,133.332 MFLOPS, 1,570.133 GFLOPS, 1.57 TFLOPS, 0.00157 PFLOPS, 1.570133e-6 EFLOPS, 1.570133e-9 ZFLOPS) +
peak flops (single-precision)3,140,266,663,936 FLOPS (3,140,266,663.936 KFLOPS, 3,140,266.664 MFLOPS, 3,140.267 GFLOPS, 3.14 TFLOPS, 0.00314 PFLOPS, 3.140267e-6 EFLOPS, 3.140267e-9 ZFLOPS) +
power dissipation100 W (100,000 mW, 0.134 hp, 0.1 kW) +
power dissipation (average)70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
process28 nm (0.028 μm, 2.8e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8,192 +