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Difference between revisions of "freescale/qoriq/p1010"
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{{freescale title|QorIQ P1010}}
 
{{freescale title|QorIQ P1010}}
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{{mpu
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{{chip
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|name=P1010
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|name=QorIQ P1010
 
|image=qoriq p1010.png
 
|image=qoriq p1010.png
 
|designer=Freescale
 
|designer=Freescale
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|series=P1
 
|series=P1
 
|frequency=667 MHz
 
|frequency=667 MHz
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|isa=Power ISA 2.03
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|frequency 2=800 MHz
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|isa=Power ISA v2.03
 
|isa family=Power
 
|isa family=Power
 
|microarch=e500
 
|microarch=e500
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|core name=e500
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|core name=e500 v2
 
|process=45 nm
 
|process=45 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=1
 
|core count=1
 
|thread count=1
 
|thread count=1
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|power=1.6 W
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|tjunc min=0 °C
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|tjunc max=125 °C
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
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|package module 2={{packages/freescale/te-pbga-425}}
 
}}
 
}}
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'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR2/3 memory.
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'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR3-800 memory.
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== Cache ==
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{{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}}
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{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=1x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=
 +
|l2 cache=
 +
|l2 break=
 +
|l2 desc=
 +
|l2 policy=
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-800
 +
|ecc=Yes
 +
|controllers=1
 +
|channels=1
 +
|width=32 bit
 +
|max bandwidth=2.98 GiB/s
 +
|bandwidth schan=2.98 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
* 2x 10/100/1000 Eithernet with SGMII
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* 2x PCIe 1.0a controllers with 2 SerDes
 +
* 2x USB 2.0
 +
* SD/MMC
 +
* SPI
 +
* 2x I2C
 +
* UART
 +
* SEC 3.1 Security Acceleration
 +
 
 +
== Block Diagram ==
 +
: [[File:qoriq p1010 block diagram.png|800px]]
 +
 
 +
== Documents ==
 +
* [[:File:QorIQ P1.pdf|QorIQ P1 Series Product Brief]]

Latest revision as of 15:13, 13 December 2017

Edit Values
QorIQ P1010
qoriq p1010.png
General Info
DesignerFreescale
ManufacturerIBM
Model NumberP1010
MarketNetworking, Embedded
IntroductionJune 16, 2008 (announced)
2009 (launched)
General Specs
FamilyQorIQ
SeriesP1
Frequency667 MHz, 800 MHz
Microarchitecture
ISAPower ISA v2.03 (Power)
Microarchitecturee500
Core Namee500 v2
Process45 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Electrical
Power dissipation1.6 W
Tjunction0 °C – 125 °C
Packaging
PackageTE-PBGA-II-689 (TE PBGA-II)
Temperature-Enhanced Plastic BGA
Dimension31 mm x 31 mm
Contacts689
PackageTE-PBGA-425 (TE PBGA)
Temperature-Enhanced Plastic BGA
Dimension19 mm x 19 mm
Pitch0.8 mm
Contacts425

QorIQ P1010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 667 MHz and supports 32-bit DDR3-800 memory.

Cache[edit]

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s

Expansions[edit]

  • 2x 10/100/1000 Eithernet with SGMII
  • 2x PCIe 1.0a controllers with 2 SerDes
  • 2x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.1 Security Acceleration

Block Diagram[edit]

qoriq p1010 block diagram.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p1010&oldid=70337"
Facts about "QorIQ P1010 - Freescale"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
QorIQ P1010 - Freescale#package +
base frequency667 MHz (0.667 GHz, 667,000 kHz) + and 800 MHz (0.8 GHz, 800,000 kHz) +
core count1 +
core namee500 v2 +
designerFreescale +
familyQorIQ +
first announcedJune 16, 2008 +
first launched2009 +
full page namefreescale/qoriq/p1010 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaPower ISA v2.03 +
isa familyPower +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
ldate2009 +
main imageFile:qoriq p1010.png +
manufacturerIBM +
market segmentNetworking + and Embedded +
max junction temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
microarchitecturee500 +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberP1010 +
nameQorIQ P1010 +
packageTE-PBGA-II-689 + and TE-PBGA-425 +
power dissipation1.6 W (1,600 mW, 0.00215 hp, 0.0016 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
seriesP1 +
supported memory typeDDR3-800 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +