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Difference between revisions of "hisilicon/kirin/970"
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{{hisil title|Kirin 970}}
 
{{hisil title|Kirin 970}}
−
{{mpu
+
{{chip
 
|name=Kirin 970
 
|name=Kirin 970
 
|image=kirin 970.png
 
|image=kirin 970.png
Line 7: Line 7:
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|model number=970
 
|model number=970
 +
|part number=Hi3670
 
|market=Mobile
 
|market=Mobile
 
|first announced=September 1, 2017
 
|first announced=September 1, 2017
Line 23: Line 24:
 
|transistors=5,500,000,000
 
|transistors=5,500,000,000
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=96.72 mm²
 +
|die length=9.75 mm
 +
|die width=9.92 mm
 
|word size=64 bit
 
|word size=64 bit
 
|core count=8
 
|core count=8
 
|thread count=8
 
|thread count=8
 
|max cpus=1
 
|max cpus=1
−
|max memory=6 GiB
+
|max memory=8 GiB
 
}}
 
}}
−
'''Kirin 970''' is a {{arch|64}} [[octa-core]] high-performance mobile [[ARM]] [[LTE]] SoC introduced by [[HiSilicon]] in mid-2017 at the [[2017 IFA]]. This chip, which is fabricated on a [[10 nm process]], features four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.36 GHz along with four {{armh|Cortex-A53}} [[little cores]] operating at up to 1.8 GHz. The 970 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali G72}} (12 core) IGP operating at 850 MHz and supports up to 6 GiB of dual-channel LPDDR4-1866 memory.
+
'''Kirin 970''' is a {{arch|64}} [[octa-core]] high-performance mobile [[ARM]] [[LTE]] SoC introduced by [[HiSilicon]] in mid-2017 at the [[2017 IFA]]. This chip, which is fabricated on a [[10 nm process]], features four {{armh|Cortex-A73|l=arch}} [[big cores]] operating at up to 2.36 GHz along with four {{armh|Cortex-A53}} [[little cores]] operating at up to 1.8 GHz. The 970 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali G72}} (12 core) IGP operating at 850 MHz and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory.
  
 
== Overview ==
 
== Overview ==
Line 36: Line 40:
 
== Cache ==
 
== Cache ==
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a73#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A73 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a73#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A73 § Cache}}
−
{{cache size}}
+
 
−
{{expand section}}
+
For the {{armh|Cortex-A73|l=arch}}:
 +
 
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
}}
 +
 
 +
For the {{armh|Cortex-A53|l=arch}}:
 +
 
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l2 cache=1 MiB
 +
|l2 break=1x1 MiB
 +
}}
  
 
== Memory controller ==
 
== Memory controller ==
 +
The Kirin 970 supports 4-channel LPDDR4X up to 1866 MHz. Each channel supports at most two ranks.
 +
 
{{memory controller
 
{{memory controller
−
|type=LPDDR4-1866
+
|type=LPDDR4X-3732
 
|ecc=No
 
|ecc=No
−
|max mem=6 GiB
+
|max mem=8 GiB
 
|controllers=1
 
|controllers=1
−
|channels=2
+
|channels=4
−
|width=64 bit
+
|width=16 bit
 
|max bandwidth=27.82 GiB/s
 
|max bandwidth=27.82 GiB/s
−
|bandwidth schan=13.91 GiB/s
+
|bandwidth dchan=13.91 GiB/s
−
|bandwidth dchan=27.82 GiB/s
+
|bandwidth qchan=27.82 GiB/s
 
}}
 
}}
  
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| max displays        = 2
 
| max displays        = 2
 
| max memory          =  
 
| max memory          =  
−
| frequency          = 850 MHz
+
| frequency          = 746 MHz
 
| max frequency      =  
 
| max frequency      =  
  
Line 74: Line 102:
 
| opengl es ver      = 3.2
 
| opengl es ver      = 3.2
 
| openvg ver        = 1.1
 
| openvg ver        = 1.1
−
| opencl ver        = 2.0
+
| opencl ver        = 1.2
 
| vulkan ver        = 1.0
 
| vulkan ver        = 1.0
 
}}
 
}}
  
−
* Hardware Acceleration
+
{| class="wikitable"
−
** Decode: 2160p @ 60fps
+
|-
−
** Encode: 2160p @ 30fps
+
! colspan="8" | Hardware Accelerated Video Capabilities
 +
|-
 +
! rowspan="2" | Codec !! colspan="3" | Encode !! colspan="3" | Decode
 +
|-
 +
! Profiles !! Levels !! Max Resolution !! Profiles !! Levels !! Max Resolution
 +
|-
 +
| [[MPEG-2]] (H.262) || colspan="3" {{tchk|no}} || Main || High || 1080p (1920 x 1080)<br> 80 Mbit/s or 60 fps
 +
|-
 +
| [[MPEG-4 AVC]] (H.264) || Baseline, High || 5.1 || 3840×2160<br>720p@240 fps || High || 5.0 || 4K x 2K (3840 x 2160)<br>135 Mbit/s or 4K x 2K@30 fps
 +
|-
 +
| [[HEVC]] (H.265) || Main || Main || 3840×2160<br>720p@240 fps || Main || 5.1 || 4K x 2K (3840 x 2160)<br>160 Mbit/s or 4K x 2K@60 fps
 +
|-
 +
| [[VC-1]] || colspan="3" {{tchk|no}} || Simple, Main, Advanced || M, H, 3 || 1080p (1920 x 1080)<br>45 Mbit/s or 60 fps
 +
|-
 +
| [[VP6]] || colspan="3" {{tchk|no}} || || || 1080p (1920 x 1080)<br>50 Mbit/s or 60 fps
 +
|-
 +
| [[VP8]] || colspan="3" {{tchk|no}} || || || 1080p (1920 x 1080)<br>50 Mbit/s or 60 fps
 +
|-
 +
| [[VP9]] || colspan="3" {{tchk|no}} || 2 || || 4K x 2K (3840 x 2160)<br>100 Mbit/s or 4K x 2K@60 fps
 +
|}
  
 
== Wireless ==
 
== Wireless ==
Line 90: Line 137:
 
* Bluetooth 4.2
 
* Bluetooth 4.2
 
* NFC
 
* NFC
−
* GPS / A-GPS / GLONASS / BDS / Galileo
+
* GPS / A-GPS / GLONASS / BDS
  
 
== Expansions ==
 
== Expansions ==
Line 98: Line 145:
 
== Neural Network Processing Unit (NPU) ==
 
== Neural Network Processing Unit (NPU) ==
 
[[File:kirin 970 npu.png|right|350px]]
 
[[File:kirin 970 npu.png|right|350px]]
−
The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Mr. Richard Yu who introduced the Kirin 970 at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 [[TFLOP]]s (HP 16-bit). While the exact architectural detials of the NPU have been withheld, the NPU appear to be a licensed IP design from [[Cambricon Technologies]].
+
The Kirin 970 incorporates a new [[neural processor|Neural Network Processing Unit]] (NPU) designed specifically to be used as an AI accelerator. According to CEO Richard Yu, who also introduced the processor at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 [[TFLOP]]s (HP 16-bit) through 256 MAC/cycleS. While the exact architectural details of the NPU have been withheld, the NPU appear to be a licensed IP design from [[Cambricon Technologies]].
  
 
== Utilizing devices ==
 
== Utilizing devices ==
 
* [[used by::Huawei Mate 10]]
 
* [[used by::Huawei Mate 10]]
 +
* [[used by::Huawei Mate 10 Pro]]
 +
* [[used by::Huawei Mate 10 Porsche Design]]
 +
* [[used by::Huawei Mate RS Porsche Design]]
 +
* [[used by::Huawei P20]]
 +
* [[used by::Huawei P20 Pro]]
 +
* [[used by::Huawei Nova 3]]
 +
* [[used by::Huawei Nova 4]]
 +
* [[used by::Honor V10 (Honor View 10)]]
 +
* [[used by::Honor 10]]
 +
* [[used by::Honor Play 2]]
 +
* [[used by::Honor Note 10]]
 +
* [[used by::HiKey 970]]
 +
* [[used by::Honor 8 Pro]]
 +
* [[used by::Honor Play]]
 +
{{expand list}}
  
−
{{expand list}}
+
== Documents ==
 +
* [[:File:hi3670-v100-ds.pdf|Hi3670 Data Sheet]]
 +
 
 +
== Bibliography ==
 +
* Huawei Kirin 970 Keynote, 2017 IFA

Latest revision as of 16:25, 1 January 2022

Edit Values
Kirin 970
kirin 970.png
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model Number970
Part NumberHi3670
MarketMobile
IntroductionSeptember 1, 2017 (announced)
September 1, 2017 (launched)
General Specs
FamilyKirin
Series900
Frequency1,800 MHz, 2,360 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53, Cortex-A73
Core NameCortex-A53, Cortex-A73
Process10 nm
Transistors5,500,000,000
TechnologyCMOS
Die96.72 mm²
9.75 mm × 9.92 mm
Word Size64 bit
Cores8
Threads8
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)

Kirin 970 is a 64-bit octa-core high-performance mobile ARM LTE SoC introduced by HiSilicon in mid-2017 at the 2017 IFA. This chip, which is fabricated on a 10 nm process, features four Cortex-A73 big cores operating at up to 2.36 GHz along with four Cortex-A53 little cores operating at up to 1.8 GHz. The 970 incorporates ARM's Mali G72 (12 core) IGP operating at 850 MHz and supports up to 8 GiB of quad-channel LPDDR4X-3732 memory.

Overview[edit]

Introduced at the 2017 IFA, the overall core organization is identical to the Kirin 960 which was introduced the previous year, but features 20% power efficiency and 40% smaller die area due to the process shrink. The 970 ballooned to over 37.5% more transistors from 4 billion in the 960 to 5.5 billion. The 970 adds many enhancements, including a more powerful Mali G72 GPU and incorporates a new Neural Network Processing Unit (NPU) designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 18 capable of reaching a maximum downlink of 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA).

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A73 § Cache


For the Cortex-A73:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB  
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

For the Cortex-A53:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB  

Memory controller[edit]

The Kirin 970 supports 4-channel LPDDR4X up to 1866 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3732
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth27.82 GiB/s
28,487.68 MiB/s
29.871 GB/s
29,871.498 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Double 13.91 GiB/s
Quad 27.82 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G72
DesignerARM Holdings
Execution Units12Max Displays2
Frequency746 MHz
0.746 GHz
746,000 KHz
OutputDSI
Standards
DirectX12
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0
Hardware Accelerated Video Capabilities
Codec Encode Decode
Profiles Levels Max Resolution Profiles Levels Max Resolution
MPEG-2 (H.262) ✘ Main High 1080p (1920 x 1080)
80 Mbit/s or 60 fps
MPEG-4 AVC (H.264) Baseline, High 5.1 3840×2160
720p@240 fps 		High 5.0 4K x 2K (3840 x 2160)
135 Mbit/s or 4K x 2K@30 fps
HEVC (H.265) Main Main 3840×2160
720p@240 fps 		Main 5.1 4K x 2K (3840 x 2160)
160 Mbit/s or 4K x 2K@60 fps
VC-1 ✘ Simple, Main, Advanced M, H, 3 1080p (1920 x 1080)
45 Mbit/s or 60 fps
VP6 ✘ 1080p (1920 x 1080)
50 Mbit/s or 60 fps
VP8 ✘ 1080p (1920 x 1080)
50 Mbit/s or 60 fps
VP9 ✘ 2 4K x 2K (3840 x 2160)
100 Mbit/s or 4K x 2K@60 fps

Wireless[edit]

  • LTE Modem
    • Up to User Equipment (UE) category 18
      • Downlink of up to 1.2 Gbps (4x4 MIMO, 256 QAM, 3CC CA)
      • Uplink of up to 150 Mbps (2x20MHz CA, 64-QAM)
  • Wi-Fi 802.11 ac Dual Band
  • Bluetooth 4.2
  • NFC
  • GPS / A-GPS / GLONASS / BDS

Expansions[edit]

Neural Network Processing Unit (NPU)[edit]

kirin 970 npu.png

The Kirin 970 incorporates a new Neural Network Processing Unit (NPU) designed specifically to be used as an AI accelerator. According to CEO Richard Yu, who also introduced the processor at 2017 IFA, the NPU uses up the die area of roughly half of the CPU while consuming 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 TFLOPs (HP 16-bit) through 256 MAC/cycleS. While the exact architectural details of the NPU have been withheld, the NPU appear to be a licensed IP design from Cambricon Technologies.

Utilizing devices[edit]

  • Huawei Mate 10
  • Huawei Mate 10 Pro
  • Huawei Mate 10 Porsche Design
  • Huawei Mate RS Porsche Design
  • Huawei P20
  • Huawei P20 Pro
  • Huawei Nova 3
  • Huawei Nova 4
  • Honor V10 (Honor View 10)
  • Honor 10
  • Honor Play 2
  • Honor Note 10
  • HiKey 970
  • Honor 8 Pro
  • Honor Play

This list is incomplete; you can help by expanding it.

Documents[edit]

Bibliography[edit]

  • Huawei Kirin 970 Keynote, 2017 IFA
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kirin/970&oldid=99640"
Facts about "Kirin 970 - HiSilicon"
RDF feed
has ecc memory supportfalse +
integrated gpuMali-G72 +
integrated gpu base frequency850 MHz (0.85 GHz, 850,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units12 +
max memory bandwidth27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels2 +
supported memory typeLPDDR4-1866 +
used byHuawei Mate 10 +