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Difference between revisions of "hisilicon/k3/k3v1"
< hisilicon‎ | k3

(Undo revision 78976 by 24.168.200.123 (talk) I don't think this is correct)
 
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{{hisilicon title|K3V1}}
 
{{hisilicon title|K3V1}}
−
{{mpu
+
{{chip
 
|name=K3V1
 
|name=K3V1
 
|no image=Yes
 
|no image=Yes
 
|designer=HiSilicon
 
|designer=HiSilicon
 +
|designer 2=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|model number=K3V1
 
|model number=K3V1
Line 23: Line 24:
 
|thread count=1
 
|thread count=1
 
|max cpus=1
 
|max cpus=1
 +
|v io=1.8 V
 +
|v io 2=2.5 V
 
|package module 1={{packages/hisilicon/tfbga-460}}
 
|package module 1={{packages/hisilicon/tfbga-460}}
 
}}
 
}}
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/arm9#Memory_Hierarchy|l1=ARM9 § Cache}}
 +
{{cache size
 +
|l1 cache = 32 KiB
 +
|l1i cache=16 KiB
 +
|l1i break=1x16 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=16 KiB
 +
|l1d break=1x16 KiB
 +
|l1d desc=4-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR
 +
|controllers=1
 +
|channels=1
 +
|width=16 bit
 +
|width 2=32 bit
 +
}}
 +
 +
== Expansions ==
 +
* 4x high-speed UART interfaces
 +
* 2x SPI
 +
* 2x I2C
 +
* USB 2.0 On-The-Go (HS OTG) PHY
 +
* USB 1.1
 +
* 2x MMC/SD/SDIO interface
 +
* 14x GPIOs
 +
* 8 Timers
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=No
 +
|trustzone=No
 +
|jazelle=Yes
 +
|wmmx=No
 +
|wmmx2=No
 +
}}
 +
 +
== Graphics ==
 +
The K3V1 integrated graphics engine, although the exact specs are not available.
 +
 +
* Support QVGA, WQVGA, VGA display resolutions
 +
* Hardware-acceleration video
 +
** Decode: [[MPEG4]], [[H.263]], [[H.264]], and [[VC-1]]
 +
*** Rate QCIF/CIF/QVGA/VGA/D1, frame rate up to 30fps
 +
** Encode: MPEG4 and H.263 video encoding
 +
*** QCIF/CIF/QVGA/VGA, frame rate up to 30fps
 +
* 200 KiB Frame Buffer
 +
 +
== Camera ==
 +
* Support 30 million pixel camera, up to 30fps
 +
* Supports up to 8 megapixel CMOS Sensor image input
 +
 +
== Audio ==
 +
* Built-in high-performance audio CODEC
 +
** Sampling frequency support 44.1kHz and 48kHz
 +
** support for sound playback and recording
 +
* High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
 +
** ADC, CODEC support any audio mixing, independent of the amplifier Output gain control
 +
 +
== Block Diagram ==
 +
[[File:hisilicon k3v1 block.png|700px]]
 +
 +
== Documents ==
 +
* [[:File:k3v1 prod brief.pdf|K3V1 Product Brief]]

Latest revision as of 20:30, 3 June 2018

Edit Values
K3V1
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberK3V1
Part NumberHi3611
MarketMobile
IntroductionJune, 2008 (announced)
June, 2008 (launched)
General Specs
FamilyK3
Frequency460
Microarchitecture
ISAARMv5 (ARM)
MicroarchitectureARM9
Core NameARM926EJ-S
Process0.18 µm
Transistors200,000,000
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
VI/O1.8 V, 2.5 V
Packaging
PackageTFBGA-460 (BGA)
Dimension14 mm x 14 mm
Pitch0.5 mm
Pins460

K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Cache[edit]

Main article: ARM9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
32,768 B
0.0313 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR
Controllers1
Channels1
Width16 bit, 32 bit

Expansions[edit]

  • 4x high-speed UART interfaces
  • 2x SPI
  • 2x I2C
  • USB 2.0 On-The-Go (HS OTG) PHY
  • USB 1.1
  • 2x MMC/SD/SDIO interface
  • 14x GPIOs
  • 8 Timers

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
JazelleDirect Bytecode eXecution

Graphics[edit]

The K3V1 integrated graphics engine, although the exact specs are not available.

  • Support QVGA, WQVGA, VGA display resolutions
  • Hardware-acceleration video
    • Decode: MPEG4, H.263, H.264, and VC-1
      • Rate QCIF/CIF/QVGA/VGA/D1, frame rate up to 30fps
    • Encode: MPEG4 and H.263 video encoding
      • QCIF/CIF/QVGA/VGA, frame rate up to 30fps
  • 200 KiB Frame Buffer

Camera[edit]

  • Support 30 million pixel camera, up to 30fps
  • Supports up to 8 megapixel CMOS Sensor image input

Audio[edit]

  • Built-in high-performance audio CODEC
    • Sampling frequency support 44.1kHz and 48kHz
    • support for sound playback and recording
  • High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
    • ADC, CODEC support any audio mixing, independent of the amplifier Output gain control

Block Diagram[edit]

hisilicon k3v1 block.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v1&oldid=78979"
Facts about "K3V1 - HiSilicon"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
K3V1 - HiSilicon#package +
base frequency460 MHz (0.46 GHz, 460,000 kHz) +
core count1 +
core nameARM926EJ-S +
designerHiSilicon + and ARM Holdings +
familyK3 +
first announcedJune 2008 +
first launchedJune 2008 +
full page namehisilicon/k3/k3v1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 2.5 V (25 dV, 250 cV, 2,500 mV) +
isaARMv5 +
isa familyARM +
l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
ldateJune 2008 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory channels1 +
microarchitectureARM9 +
model numberK3V1 +
nameK3V1 +
packageTFBGA-460 +
part numberHi3611 +
process180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways1 +
supported memory typeDDR +
technologyCMOS +
thread count1 +
transistor count200,000,000 +
word size32 bit (4 octets, 8 nibbles) +