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K3V1 - HiSilicon
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K3V1
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberK3V1
Part NumberHi3611
MarketMobile
IntroductionJune, 2008 (announced)
June, 2008 (launched)
General Specs
FamilyK3
Frequency460
Microarchitecture
ISAARMv5 (ARM)
MicroarchitectureARM9
Core NameARM926EJ-S
Process0.18 µm
Transistors200,000,000
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
VI/O1.8 V, 2.5 V
Packaging
PackageTFBGA-460 (BGA)
Dimension14 mm x 14 mm
Pitch0.5 mm
Pins460

K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Cache[edit]

Main article: ARM9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
L1I$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1x16 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
1x16 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR
Controllers1
Channels1
Width16 bit, 32 bit

Expansions[edit]

  • 4x high-speed UART interfaces
  • 2x SPI
  • 2x I2C
  • USB 2.0 On-The-Go (HS OTG) PHY
  • USB 1.1
  • 2x MMC/SD/SDIO interface
  • 14x GPIOs
  • 8 Timers

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
JazelleDirect Bytecode eXecution

Graphics[edit]

The K3V1 integrated graphics engine, although the exact specs are not available.

  • Support QVGA, WQVGA, VGA display resolutions
  • Hardware-acceleration video
    • Decode: MPEG4, H.263, H.264, and VC-1
      • Rate QCIF/CIF/QVGA/VGA/D1, frame rate up to 30fps
    • Encode: MPEG4 and H.263 video encoding
      • QCIF/CIF/QVGA/VGA, frame rate up to 30fps
  • 200 KiB Frame Buffer

Camera[edit]

  • Support 30 million pixel camera, up to 30fps
  • Supports up to 8 megapixel CMOS Sensor image input

Audio[edit]

  • Built-in high-performance audio CODEC
    • Sampling frequency support 44.1kHz and 48kHz
    • support for sound playback and recording
  • High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
    • ADC, CODEC support any audio mixing, independent of the amplifier Output gain control

Block Diagram[edit]

hisilicon k3v1 block.png

Documents[edit]

Facts about "K3V1 - HiSilicon"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
K3V1 - HiSilicon#package +
base frequency460 MHz (0.46 GHz, 460,000 kHz) +
core count1 +
core nameARM926EJ-S +
designerHiSilicon + and ARM Holdings +
familyK3 +
first announcedJune 2008 +
first launchedJune 2008 +
full page namehisilicon/k3/k3v1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 2.5 V (25 dV, 250 cV, 2,500 mV) +
isaARMv5 +
isa familyARM +
l1$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
l1d$ description4-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
ldateJune 2008 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory channels1 +
microarchitectureARM9 +
model numberK3V1 +
nameK3V1 +
packageTFBGA-460 +
part numberHi3611 +
process180 nm (0.18 μm, 1.8e-4 mm) +
smp max ways1 +
supported memory typeDDR +
technologyCMOS +
thread count1 +
transistor count200,000,000 +
word size32 bit (4 octets, 8 nibbles) +