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Difference between revisions of "intel/xeon w/w-2155"
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{{intel title|Xeon W-2155}}
 
{{intel title|Xeon W-2155}}
−
{{mpu
+
{{chip
−
|future=Yes
 
 
|name=Xeon W-2155
 
|name=Xeon W-2155
 
|image=intel skylake w (front).png
 
|image=intel skylake w (front).png
Line 9: Line 8:
 
|part number=CD8067303533703
 
|part number=CD8067303533703
 
|s-spec=SR3LR
 
|s-spec=SR3LR
 +
|s-spec qs=QMVT
 
|market=Workstation
 
|market=Workstation
 
|first announced=August 29, 2017
 
|first announced=August 29, 2017
 
|first launched=August 29, 2017
 
|first launched=August 29, 2017
−
|release price=$1440.00
+
|release price (tray)=$1440.00
 
|family=Xeon W
 
|family=Xeon W
 
|series=W-2000
 
|series=W-2000
Line 25: Line 25:
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake (server)
 
|microarch=Skylake (server)
−
|platform=Purley
+
|platform=Basin Falls
 
|core name=Skylake W
 
|core name=Skylake W
 
|core family=6
 
|core family=6
Line 37: Line 37:
 
|max memory=512 GiB
 
|max memory=512 GiB
 
|tdp=140 W
 
|tdp=140 W
−
|package module 1={{packages/intel/fclga-2066}}
+
|tcase min=0 °C
 +
|tcase max=68 °C
 +
|package name 1=intel,fclga_2066
 
}}
 
}}
 
'''W-2155''' is a {{arch|64}} [[deca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.3 GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
 
'''W-2155''' is a {{arch|64}} [[deca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.3 GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
Line 73: Line 75:
 
|bandwidth dchan=39.74 GiB/s
 
|bandwidth dchan=39.74 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 +
|pae=46 bit
 
}}
 
}}
  
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|pcie config 3=x4
 
|pcie config 3=x4
 
}}
 
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=2
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,300 MHz
 +
|freq_1=4,500 MHz
 +
|freq_2=4,500 MHz
 +
|freq_3=4,300 MHz
 +
|freq_4=4,300 MHz
 +
|freq_5=4,200 MHz
 +
|freq_6=4,200 MHz
 +
|freq_7=4,200 MHz
 +
|freq_8=4,200 MHz
 +
|freq_9=4,000 MHz
 +
|freq_10=4,000 MHz
 +
|freq_avx2_1=4,000 MHz
 +
|freq_avx2_2=4,000 MHz
 +
|freq_avx2_3=3,800 MHz
 +
|freq_avx2_4=3,800 MHz
 +
|freq_avx2_5=3,700 MHz
 +
|freq_avx2_6=3,700 MHz
 +
|freq_avx2_7=3,700 MHz
 +
|freq_avx2_8=3,700 MHz
 +
|freq_avx2_9=3,600 MHz
 +
|freq_avx2_10=3,600 MHz
 +
|freq_avx512_1=4,000 MHz
 +
|freq_avx512_2=4,000 MHz
 +
|freq_avx512_3=3,800 MHz
 +
|freq_avx512_4=3,800 MHz
 +
|freq_avx512_5=3,500 MHz
 +
|freq_avx512_6=3,500 MHz
 +
|freq_avx512_7=3,500 MHz
 +
|freq_avx512_8=3,500 MHz
 +
|freq_avx512_9=3,300 MHz
 +
|freq_avx512_10=3,300 MHz
 
}}
 
}}

Latest revision as of 14:22, 3 July 2019

Edit Values
Xeon W-2155
intel skylake w (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberW-2155
Part NumberCD8067303533703
S-SpecSR3LR
QMVT (QS)
MarketWorkstation
IntroductionAugust 29, 2017 (announced)
August 29, 2017 (launched)
Release Price$1440.00 (tray)
ShopAmazon
General Specs
FamilyXeon W
SeriesW-2000
LockedYes
Frequency3,300 MHz
Turbo Frequency4,500 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier33
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformBasin Falls
Core NameSkylake W
Core Family6
Core SteppingU0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads20
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP140 W
Tcase0 °C – 68 °C
Packaging
PackageFCLGA-2066 (LGA)
Dimension52.5 mm × 45 mm
Pitch1.016 mm
Contacts2066
SocketSocket R4

W-2155 is a 64-bit deca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.3 GHz with a TDP of 140 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associative 
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back
L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  10x1 MiB16-way set associativewrite-back
L3$13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
  10x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Physical Address (PAE)46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
IPTIdentity Protection Technology

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678910
Normal3,300 MHz4,500 MHz4,500 MHz4,300 MHz4,300 MHz4,200 MHz4,200 MHz4,200 MHz4,200 MHz4,000 MHz4,000 MHz
AVX24,000 MHz4,000 MHz3,800 MHz3,800 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,600 MHz3,600 MHz
AVX5124,000 MHz4,000 MHz3,800 MHz3,800 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_w/w-2155&oldid=92299"
Facts about "Xeon W-2155 - Intel"
RDF feed
has ecc memory supporttrue +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description16-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description11-way set associative +
l3$ size13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
max memory bandwidth79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
supported memory typeDDR4-2666 +