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(add stepping (kbl-r and cfl has the same CPUID, they just plus 1 stepping from the kbl))
 
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|proc=14 nm
 
|proc=14 nm
 
|tech=CMOS
 
|tech=CMOS
 +
|clock min=1,600 MHz
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|clock max=1,900 MHz
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|package module 1={{packages/intel/fcbga-1356}}
 
|predecessor=Kaby Lake U
 
|predecessor=Kaby Lake U
 
|predecessor link=intel/cores/kaby lake u
 
|predecessor link=intel/cores/kaby lake u
−
|successor=Coffee Lake U
+
|successor=Whiskey Lake U
−
|successor link=intel/cores/coffee lake u
+
|successor link=intel/cores/whiskey lake u
 +
|successor 2=Cannon Lake U
 +
|successor 2 link=intel/cores/cannon lake u
 
}}
 
}}
 
'''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]] and feature double the core count of the previous generation.
 
'''Kaby Lake R''' ('''KBL-R''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a refresh to {{intel|Kaby Lake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced [[14 nm lithography process|14nm+ process]] and feature double the core count of the previous generation.
 +
 +
Although those microprocessors are still based on {{intel|Kaby Lake|l=arch}}, Intel has branded them as 8th Generation Core. Those processors are also the first to feature quad-cores within the 15 Watt TDP class of mobile processors.
  
 
== Overview ==
 
== Overview ==
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* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
 
* Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
 
* {{intel|Turbo Boost}}, {{intel|Hyper-Threading}}, {{intel|Software Guard}}, {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|OS Guard}}, {{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
 
* {{intel|Turbo Boost}}, {{intel|Hyper-Threading}}, {{intel|Software Guard}}, {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|OS Guard}}, {{intel|Flex Memory}}, {{intel|My WiFi Technology}}, and {{intel|Identity Protection Technology}}
−
* Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
+
* Support [[AHCI]], [[High Definition Audio]], 6x [[USB 3.0]] ports, 10x [[USB 2.0]] ports, 4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
 
* Graphics
 
* Graphics
−
** {{intel|HD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2)
+
** {{intel|UHD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2)
 
** 3 independent displays supported
 
** 3 independent displays supported
 
** Base frequency of 300 MHz
 
** Base frequency of 300 MHz
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{{clear}}
 
{{clear}}
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[ICC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 +
|-
 +
| [[GCC]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 +
|-
 +
| [[LLVM]] || <code>-march=skylake</code> || <code>-mtune=skylake</code>
 +
|-
 +
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:skylake</code>
 +
|}
 +
 +
=== CPUID ===
 +
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
 +
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
 +
|-
 +
| rowspan="2" | {{intel|Kaby Lake R|U|l=core}} || 0 || 0x6 || 0x8 || 0xE || 0xA
 +
|-
 +
| colspan="5" | Family 6 Model 142 Stepping 10
 +
|}
 +
  
 
== Kaby Lake R Processors ==
 
== Kaby Lake R Processors ==
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</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
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 +
== Documents ==
 +
* [[:File:kaby-lake-r-product-brief.pdf|Kaby Lake R Product Brief]]
  
 
== See also ==
 
== See also ==

Latest revision as of 08:52, 11 February 2019

Edit Values
Kaby Lake R
kaby lake r (front).png
Package front side
kaby lake r (back).png
Package back side
General Info
DesignerIntel
ManufacturerIntel
IntroductionAugust 21, 2017 (announced)
August 21, 2017 (launched)
Microarchitecture
ISAx86-64
MicroarchitectureKaby Lake
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
TechnologyCMOS
Clock1,600 MHz - 1,900 MHz
Packaging
PackageFCBGA-1356 (BGA)
Dimension42 mm x 24 mm x 1.3 mm
Pitch0.65 mm
Ball Count1356
Ball CompSAC405
InterconnectBGA-1356
Succession

Kaby Lake R (KBL-R) is the name of the core for Intel's line of low-power mobile processors based on the Kaby Lake microarchitecture serving as a refresh to Kaby Lake U. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake R processors are fabricated on Intel's 2nd generation enhanced 14nm+ process and feature double the core count of the previous generation.

Although those microprocessors are still based on Kaby Lake, Intel has branded them as 8th Generation Core. Those processors are also the first to feature quad-cores within the 15 Watt TDP class of mobile processors.

Overview[edit]

Kaby Lake R based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a multi-chip package (MCP). Unlike Kaby Lake U, there are no variations with 3 dies which incorporated an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Kaby Lake R processors use Socket BGA-1356.

Common Features[edit]

All Kaby Lake R processors have the following:

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model Stepping
U 0 0x6 0x8 0xE 0xA
Family 6 Model 142 Stepping 10


Kaby Lake R Processors[edit]

 List of Kaby Lake R Processors
 Main processorIGP
ModelLaunchedPriceFamilyCoresThreadsL3$TDPFrequencyTurboMax MemNameFrequencyTurbo
i5-8250U21 August 2017$ 297.00
€ 267.30
£ 240.57
¥ 30,689.01
Core i5486 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.6 GHz
1,600 MHz
1,600,000 kHz
3.4 GHz
3,400 MHz
3,400,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
UHD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i5-8350U21 August 2017$ 297.00
€ 267.30
£ 240.57
¥ 30,689.01
Core i5486 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.7 GHz
1,700 MHz
1,700,000 kHz
3.6 GHz
3,600 MHz
3,600,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
UHD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,100 MHz
1.1 GHz
1,100,000 KHz
i7-8550U21 August 2017$ 409.00
€ 368.10
£ 331.29
¥ 42,261.97
Core i7488 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.8 GHz
1,800 MHz
1,800,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
UHD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
i7-8650U21 August 2017$ 409.00
€ 368.10
£ 331.29
¥ 42,261.97
Core i7488 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
15 W
15,000 mW
0.0201 hp
0.015 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
4.2 GHz
4,200 MHz
4,200,000 kHz
32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
0.0313 TiB
UHD Graphics 620300 MHz
0.3 GHz
300,000 KHz
1,150 MHz
1.15 GHz
1,150,000 KHz
Count: 4

Documents[edit]

See also[edit]

kaby lake r (front, angled).png
kaby lake r (back, angled).png

arrow up 1.svgPower/Performance

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Facts about "Kaby Lake R - Cores - Intel"
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Kaby Lake R - Cores - Intel#package +
designerIntel +
first announcedAugust 21, 2017 +
first launchedAugust 21, 2017 +
instance ofcore +
isax86-64 +
main imageFile:kaby lake r (front).png + and File:kaby lake r (back).png +
main image captionPackage front side + and Package back side +
manufacturerIntel +
microarchitectureKaby Lake +
nameKaby Lake R +
packageFCBGA-1356 +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +