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{{intel title|Celeron 807UE}}
 
{{intel title|Celeron 807UE}}
−
{{mpu
+
{{chip
 
|name=Celeron 807UE
 
|name=Celeron 807UE
 
|no image=Yes
 
|no image=Yes
Line 9: Line 9:
 
|s-spec=SR0NB
 
|s-spec=SR0NB
 
|market=Embedded
 
|market=Embedded
 +
|first announced=December, 2011
 +
|first launched=July, 2012
 
|family=Celeron
 
|family=Celeron
 
|series=800
 
|series=800
Line 45: Line 47:
 
|package module 1={{packages/intel/fcbga-1023}}
 
|package module 1={{packages/intel/fcbga-1023}}
 
}}
 
}}
 +
'''Celeron 807UE''' is a [[single-core]] budget mobile embedded [[x86]] microprocessor introduced by [[Intel]] in mid-[[2012]]. The Celeron 807UE, which is based on the {{intel|Sandy Bridge|l=arch}} microarchitecture and is manufactured on a [[32 nm process]], operates at 1 GHz with an ultra-low [[TDP]] of just 10 W. This chip incorporates Intel's {{intel|HD Graphics (Sandy Bridge)|HD Graphics}} [[integrated graphics]] operating at 350 MHz with a burst frequency of 800 MHz. This processor supports 4 GiB of single-channel DDR3-1333 ECC memory.
  
 
== Cache ==
 
== Cache ==
 +
{{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}}
 +
{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=1x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=256 KiB
 +
|l2 break=1x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=1.5 MiB
 +
|l3 break=1x1.5 MiB
 +
|l3 desc=12-way set associative
 +
|l3 policy=write-back
 +
}}
  
 
== Memory controller ==
 
== Memory controller ==
Line 61: Line 83:
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions main
+
This processor has no PCIe lanes. As per datasheet:
−
|
+
 
−
{{expansions entry
+
The single core Celeron SKU Intel® Celeron® Processor 807UE does not support PCI Express in any configuration. All of the processor’s PCI Express lanes are disabled for both graphics and I/O.
−
|type=PCIe
 
−
|pcie revision=2.0
 
−
|pcie lanes=16
 
−
|pcie config=1x16
 
−
|pcie config 2=2x8
 
−
|pcie config 3=1x8+2x4
 
−
}}
 
−
}}
 
  
 
== Graphics ==
 
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = HD Graphics (Sandy Bridge)
 +
| device id          = 0x0106
 +
| designer            = Intel
 +
| execution units    = 6
 +
| max displays        = 2
 +
| frequency          = 350 MHz
 +
| max frequency      = 800 MHz
 +
 +
| output crt          = Yes
 +
| output sdvo        = Yes
 +
| output dsi          =
 +
| output edp          = Yes
 +
| output dp          = Yes
 +
| output hdmi        = Yes
 +
| output vga          =
 +
| output dvi          =
 +
 +
| directx ver        = 10.1
 +
| opengl ver        = 3.1
 +
| opencl ver        =
 +
| hdmi ver          = 1.4
 +
| dp ver            = 1.1
 +
| edp ver            = 1.1
 +
 +
| features            = Yes
 +
| intel fdi            = Yes
 +
}}
 +
{{sandy bridge hardware accelerated video table|col=1}}
  
 
== Features ==
 
== Features ==
−
{{x86 features}}
+
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=Yes
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=Yes
 +
|fastmem=Yes
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 
 +
== Documents ==
 +
=== Datasheet ===
 +
* [[:File:2nd-gen-core-family-mobile-vol-1-datasheet.pdf|Datasheet, Volume 1]]
 +
* [[:File:2nd-gen-core-family-mobile-vol-2-datasheet.pdf|Datasheet, Volume 2]]
 +
* [[:File:2nd-gen-core-mobile-ecc-datasheet-addendum.pdf|Datasheet Addendum for ECC models]]
 +
=== Other ===
 +
* [[:File:2nd-gen-core-mobile-thermal-guide.pdf|Thermal Design Guide for Embedded Applications]]
 +
* [[:File:2nd-gen-core-family-mobile-specification-update.pdf|2nd Gen Core Mobile Specification Update]]

Latest revision as of 18:19, 17 March 2018

Edit Values
Celeron 807UE
General Info
DesignerIntel
ManufacturerIntel
Model Number807UE
Part NumberAV8062701188200
S-SpecSR0NB
MarketEmbedded
IntroductionDecember, 2011 (announced)
July, 2012 (launched)
ShopAmazon
General Specs
FamilyCeleron
Series800
LockedYes
Frequency1,000 MHz
Bus typeDMI 2.0
Bus rate4 × 5 GT/s
Clock multiplier10
CPUID0x206A7
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSandy Bridge
PlatformSandy Bridge M
ChipsetCougar Point
Core NameSandy Bridge M
Core Family6
Core Model42
Core SteppingQ0
Process32 nm
Transistors504,000,000
TechnologyCMOS
Die131 mm²
Word Size64 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.3 V-1.52 V
TDP10 W
Tjunction0 °C – 100 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1023 (BGA)
Dimension31 mm x 24 mm
Pitch0.65 mm
Contacts1023

Celeron 807UE is a single-core budget mobile embedded x86 microprocessor introduced by Intel in mid-2012. The Celeron 807UE, which is based on the Sandy Bridge microarchitecture and is manufactured on a 32 nm process, operates at 1 GHz with an ultra-low TDP of just 10 W. This chip incorporates Intel's HD Graphics integrated graphics operating at 350 MHz with a burst frequency of 800 MHz. This processor supports 4 GiB of single-channel DDR3-1333 ECC memory.

Cache[edit]

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associativewrite-back
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associativewrite-back
L3$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  1x1.5 MiB12-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333, DDR3-1066
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth9.93 GiB/s
10,168.32 MiB/s
10.662 GB/s
10,662.256 MB/s
0.0097 TiB/s
0.0107 TB/s
Bandwidth
Single 9.93 GiB/s

Expansions[edit]

This processor has no PCIe lanes. As per datasheet: 

The single core Celeron SKU Intel® Celeron® Processor 807UE does not support PCI Express in any configuration. All of the processor’s PCI Express lanes are disabled for both graphics and I/O.

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUHD Graphics (Sandy Bridge)
DesignerIntelDevice ID0x0106
Execution Units6Max Displays2
Frequency350 MHz
0.35 GHz
350,000 KHz
Burst Frequency800 MHz
0.8 GHz
800,000 KHz
OutputDP, eDP, HDMI, SDVO, CRT
Standards
DirectX10.1
OpenGL3.1
DP1.1
eDP1.1
HDMI1.4
Additional Features
Intel Flexible Display Interface (FDI)

Features[edit]

Documents[edit]

Datasheet[edit]

Other[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/807ue&oldid=75284"
Facts about "Celeron 807UE - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 807UE - Intel#pcie +
has ecc memory supporttrue +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l3$ description12-way set associative +
l3$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
max memory bandwidth9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) +
max memory channels1 +
supported memory typeDDR3-1333 + and DDR3-1066 +