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{{intel title|Atom C3850}}
 
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|core model=95
 
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'''Atom C3850''' is a {{arch|64}} [[dodeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3850, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2.1 GHz with a [[TDP]] of 25 W and a {{intel|turbo boost}} frequency of up to 2.4 GHz. The C3850 supports up to a dual-channel of 256 GiB of DDR4-2133 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Server and Cloud Storage SKUs]].
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'''Atom C3850''' is a {{arch|64}} [[dodeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3850, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2.1 GHz with a [[TDP]] of 25 W and a {{intel|turbo boost}} frequency of up to 2.4 GHz. The C3850 supports up to 256 GiB of dual-channel DDR4-2133 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Server and Cloud Storage SKUs]].
  
 
== Cache ==
 
== Cache ==
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== Expansions ==
 
== Expansions ==
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This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:
 
{{expansions main
 
{{expansions main
 
|
 
|
−
{{expansions entry}}
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{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=16
 +
|pcie config=x8
 +
|pcie config 2=x4
 +
|pcie config 3=x2
 +
|pcie config 4=x1
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.0
 +
|usb ports=8
 +
}}
 +
{{expansions entry
 +
|type=HSIO
 +
|hsio lanes=20
 +
}}
 +
}}
 +
 
 +
== Networking ==
 +
{{network
 +
|eth opts=Yes
 +
|10ge=Yes
 +
|10ge ports=2
 
}}
 
}}
  

Latest revision as of 23:44, 14 August 2019

Edit Values
Atom C3850
denverton (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberC3850
Part NumberHW8076502639201
S-SpecSR387
MarketServer, Embedded
IntroductionAugust 15, 2017 (announced)
August 15, 2017 (launched)
Release Price$323.00
ShopAmazon
General Specs
FamilyAtom
Series3000
LockedYes
Frequency2,100 MHz
Turbo Frequency2,400 MHz (1 core)
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont
Core NameDenverton
Core Family6
Core Model95
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads12
Max Memory256 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP25 W
Tjunction0 °C – 100 °C
Tcase0 °C – 78 °C
Tstorage-25 °C – 125 °C
Packaging
PackageFCBGA-1310 (BGA)
Dimension34 mm x 28 mm
Ball Count1310
Ball CompSAC405
InterconnectBGA-1310

Atom C3850 is a 64-bit dodeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3850, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.1 GHz with a TDP of 25 W and a turbo boost frequency of up to 2.4 GHz. The C3850 supports up to 256 GiB of dual-channel DDR4-2133 ECC memory. This model is part of Denverton's Server and Cloud Storage SKUs.

Cache[edit]

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$672 KiB
688,128 B
0.656 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L1D$288 KiB
294,912 B
0.281 MiB
12x24 KiB6-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  6x2 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: x8, x4, x2, x1
USBRevision: 3.0
Max Ports: 8
HSIOMax Lanes: 20


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 2)

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/c3850&oldid=93380"
Facts about "Atom C3850 - Intel"
RDF feed
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Memory Protection Extensions +
has intel enhanced speedstep technologytrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size672 KiB (688,128 B, 0.656 MiB) +
l1d$ description6-way set associative +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
part ofServer and Cloud Storage SKUs +
supported memory typeDDR3L-1600 + and DDR4-2133 +
x86/has memory protection extensionstrue +