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{{intel title|Xeon Gold 6130F}} | {{intel title|Xeon Gold 6130F}} | ||
− | {{ | + | {{chip |
|name=Xeon Gold 6130F | |name=Xeon Gold 6130F | ||
|image=skylake-sp (hfi).png | |image=skylake-sp (hfi).png | ||
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|part number=CD8067303593300 | |part number=CD8067303593300 | ||
|s-spec=SR3KD | |s-spec=SR3KD | ||
− | |s-spec qs= | + | |s-spec qs=QMHX |
|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
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|release price=$2049.00 | |release price=$2049.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6100 |
|locked=Yes | |locked=Yes | ||
|frequency=2,100 MHz | |frequency=2,100 MHz | ||
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|core count=16 | |core count=16 | ||
|thread count=32 | |thread count=32 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=135 W | |tdp=135 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=87 °C | |tcase max=87 °C | ||
|dts min=0 °C | |dts min=0 °C | ||
− | |package | + | |package name 1=intel,fclga_3647 |
}} | }} | ||
'''Xeon Gold 6130F''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130F, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 135 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | '''Xeon Gold 6130F''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130F, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 135 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6130F | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6130F |
Part Number | CD8067303593300 |
S-Spec | SR3KD QMHX (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2049.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Clock multiplier | 21 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 135 W |
Tcase | 0 °C – 87 °C |
TDTS | 0 °C – |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6130F is a 64-bit 16-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130F, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 135 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
This specific model incorporates the Omni-Path Host Fabric Interface (HFI) die in the same package as the processor.
The 135 W of TDP for this microprocessor consists of 127 W for the CPU and 8 W for the fabric.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | ||
Normal | 2,100 MHz | 3,700 MHz | 3,700 MHz | 3,500 MHz | 3,500 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz |
AVX2 | 1,700 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz |
AVX512 | 1,300 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz |
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6130F - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2666 + |