Latest revision as of 15:32, 13 December 2017

R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066, DDR2-800 Supports ECC No Max Mem 1 GiB Controllers 1 Channels 1 Width 32 bit Max Bandwidth 3.97 GiB/s 4,065.28 MiB/s 4.263 GB/s 4,262.755 MB/s 0.00388 TiB/s 0.00426 TB/s Bandwidth Single 3.97 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	USB Revision 2.0 Ports 2 Rate 480 Mbps UART Ports 8 SATA Revision 3.0 Ports 1 I²C Ports 4 GP I/O Yes JTAG Yes

• MLB (MOST150) 6-Pin I/F
• 2 x CAN 32 Message Buffers
• MMC
• 3 x SD

Graphics[edit]

• 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX540 Designer Imagination Technologies Execution Units 2 Max Displays 2 Frequency 200 MHz 0.2 GHz 200,000 KHz Standards OpenGL 2.1 OpenGL ES 2.0

Block Diagram[edit]