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Difference between revisions of "renesas/r-car/m1s"
< renesas‎ | r-car

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{{renesas title|R-Car M1S}}
 
{{renesas title|R-Car M1S}}
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{{mpu
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{{chip
 
|name=R-Car M1S
 
|name=R-Car M1S
 
|no image=Yes
 
|no image=Yes
 
|designer=Renesas
 
|designer=Renesas
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|designer 2=ARM Holdings
 
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|model number=M1S
 
|model number=M1S
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|first announced=February 16, 2011
 
|first announced=February 16, 2011
 
|first launched=June, 2012
 
|first launched=June, 2012
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|release price=$70
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|release price=$65
 
|family=R-Car
 
|family=R-Car
 
|series=1st Gen
 
|series=1st Gen
 
|frequency=800 MHz
 
|frequency=800 MHz
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|isa=ARMv7
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|isa=SuperH
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|isa family=ARM
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|isa family=SuperH
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|isa 2=SuperH
 
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|isa 2 family=SuperH
 
 
|microarch=SH-4A
 
|microarch=SH-4A
 
|core name=SH-4A
 
|core name=SH-4A
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|package module 1={{packages/renesas/fcbga-472}}
 
|package module 1={{packages/renesas/fcbga-472}}
 
}}
 
}}
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'''R-Car M1S''' is a mid-range performance embedded [[single-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1S features a single {{renesas|SH-4A|l=arch}} core operating at 800 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
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'''R-Car M1S''' is a mid-range performance embedded [[single-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1S features a single {{renesas|SH-4A|l=arch}} core operating at 800 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX540}} [[GPU]] operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
  
 +
Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.
 
== Cache ==
 
== Cache ==
 
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{memory controller
 
{{memory controller
 
|type=DDR3-1066
 
|type=DDR3-1066
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|type=DDR2-800
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|type 2=DDR2-800
 
|ecc=No
 
|ecc=No
 
|max mem=1 GiB
 
|max mem=1 GiB
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}}
 
}}
  
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== Features ==  
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== Block Diagram ==
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{{arm features
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: [[File:rcar m1s block.png|650px]]
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|thumb=No
 
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|thumb2=Yes
 
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|thumbee=Yes
 
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|vfpv1=No
 
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|vfpv2=No
 
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|vfpv3=Yes
 
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|vfpv3-d16=No
 
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|vfpv3-f16=No
 
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|vfpv4=No
 
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|vfpv4-d16=No
 
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|vfpv5=No
 
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|neon=Yes
 
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|jazelle=Yes
 
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|wmmx=No
 
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|wmmx2=No
 
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}}
 

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car M1S
General Info
DesignerRenesas
ManufacturerTSMC
Model NumberM1S
Part NumberR8A77780
MarketEmbedded
IntroductionFebruary 16, 2011 (announced)
June, 2012 (launched)
Release Price$65
General Specs
FamilyR-Car
Series1st Gen
Frequency800 MHz
Microarchitecture
ISASuperH (SuperH)
MicroarchitectureSH-4A
Core NameSH-4A
Process40 nm
TechnologyCMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Vcore1.2 V
VI/O3.3 V
Packaging
PackageFCBGA-472 (BGA)
Dimension21 mm x 21 mm
Pitch0.80 mm
Ball Count472
InterconnectBGA-472

R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth3.97 GiB/s
4,065.28 MiB/s
4.263 GB/s
4,262.755 MB/s
0.00388 TiB/s
0.00426 TB/s
Bandwidth
Single 3.97 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4
GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics[edit]

  • 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency200 MHz
0.2 GHz
200,000 KHz
Standards
OpenGL2.1
OpenGL ES2.0

Block Diagram[edit]

rcar m1s block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m1s&oldid=71197"
Facts about "R-Car M1S - Renesas"
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has ecc memory supportfalse +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
max memory bandwidth3.97 GiB/s (4,065.28 MiB/s, 4.263 GB/s, 4,262.755 MB/s, 0.00388 TiB/s, 0.00426 TB/s) +
max memory channels1 +
supported memory typeDDR3-1066 + and DDR2-800 +