Latest revision as of 15:32, 13 December 2017

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R-Car H1
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	H1
Part Number	R8A77790
Market	Embedded
Introduction	October 21, 2011 (announced) November, 2011 (launched)
General Specs
Family	R-Car
Series	1st Gen
Frequency	800 MHz, 1000 MHz
Microarchitecture
ISA	ARMv7 (ARM)
Microarchitecture	Cortex-A9, SH-4A
Core Name	Cortex-A9, SH-4A
Process	40 nm
Technology	CMOS
Word Size	32 bit
Cores	5
Threads	5
Max Memory	2 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.2 V
VI/O	3.3 V
Packaging
Package FCBGA-832 (BGA) Dimension 27 mm x 27 mm Pitch 0.80 mm Ball Count 832 Interconnect BGA-832

R-Car H1 is a high-end embedded penta-core SoC for the automotive industry designed by Renesas and introduced in 2011. The H1 features 5 cores, four Cortex-A9 cores operating at 1 GHz and an additional SH-4A core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates Imagination's PowerVR SGX543-MP2 GPU. The H1 supports up to 2 GiB of dual-channel DDR3-1066 memory.

Announced in late 2011, Renesas expected mass production begin in December 2012 with a peak rate of 100,000 units per month by December 2013.

Cache[edit]

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066 Supports ECC No Max Mem 2 GiB Controllers 1 Channels 2 Width 32 bit Max Bandwidth 7.95 GiB/s 8,140.8 MiB/s 8.536 GB/s 8,536.248 MB/s 0.00776 TiB/s 0.00854 TB/s Bandwidth Single 3.97 GiB/s Double 7.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 2.0 Max Lanes 1 Configs 1x1 USB Revision 2.0 Ports 2 Rate 480 Mbps UART Ports 8 SATA Revision 3.0 Ports 1 I²C Ports 4 GP I/O Yes JTAG Yes

• 3 x HSPI
• MLB (MOST150) 6-Pin I/F
• 2 x CAN 32 Message Buffers
• MMC
• 4 x SD

Graphics[edit]

• Display out × 2 ch (RGB888)
• Video input x 2 ch
• Video decode processor (H.264/AVC, MPEG-4, VC-1)

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX543 Designer Imagination Technologies Execution Units 2 Max Displays 2 Frequency 250 MHz 0.25 GHz 250,000 KHz Standards OpenGL 2.0 OpenCL 1.1 OpenGL ES 2.0

Audio[edit]

• Sound processing unit × 2 ch
• Sampling rate converter × 10 ch
• Sound serial interface × 10 ch
• MOST DTCP

Features[edit]

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension Jazelle Direct Bytecode eXecution

Block Diagram[edit]

Dev Board ("MARZEN")[edit]

• 200 mmx 150 mm
• R-CAR H1
• 64 MiB flash memory
• 1 MiB serial flash/E²PROM
• 2 x512 MiB DDR3-DRAM
• RS-232C, UART,USB, SD, LAN, SATA, PCI, CAN, and MLB interfaces
• Analog RGB with DSUB 15-pin and/or LVDS flat cable connector
• switches,LEDs, I/O expansion