Difference between revisions of "intel/xeon silver/4114t"

	Edit Values
	Xeon Silver 4114T
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	4114T
S-Spec	SR3MM; QN7A (QS)
Market	Server
Introduction	July 11, 2017 (announced); July 11, 2017 (launched)
Shop	Amazon
	General Specs
Family	Xeon Silver
Series	4000
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	3,000 MHz (1 core)
Clock multiplier	22
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	U0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	768 GiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	9.6 GT/s
	Electrical
TDP	85 W
Tcase	0 °C – 77 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Latest revision as of 18:07, 3 August 2022

Xeon Silver 4114T is a 64-bit deca-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4114T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

640 KiB

655,360 B
0.625 MiB

L1I$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative
L1D$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative	write-back

L2$

10 MiB

10,240 KiB
10,485,760 B
0.00977 GiB

		10x1 MiB	16-way set associative	write-back

L3$

13.75 MiB

14,080 KiB
14,417,920 B
0.0134 GiB

		10x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2400
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s
Bandwidth	Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10
Normal	2,200 MHz	3,000 MHz	3,000 MHz	2,800 MHz	2,800 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,700 MHz	2,500 MHz	2,500 MHz
AVX2	1,800 MHz	2,900 MHz	2,900 MHz	2,700 MHz	2,700 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,200 MHz	2,200 MHz
AVX512	1,100 MHz	1,800 MHz	1,800 MHz	1,600 MHz	1,600 MHz	1,500 MHz	1,500 MHz	1,500 MHz	1,500 MHz	1,400 MHz	1,400 MHz

@@ Line 1: / Line 1: @@
 {{intel title|Xeon Silver 4114T}}
-{{mpu
+{{chip
 |name=Xeon Silver 4114T
 |image=skylake sp (basic).png
@@ Line 6: / Line 6: @@
 |manufacturer=Intel
 |model number=4114T
+|s-spec=SR3MM
+|s-spec qs=QN7A
 |market=Server
 |first announced=July 11, 2017
@@ Line 17: / Line 19: @@
 |isa=x86-64
 |isa family=x86
-|microarch=Skylake
+|microarch=Skylake (server)
 |platform=Purley
 |chipset=Lewisburg
 |core name=Skylake SP
 |core family=6
+|core stepping=U0
 |process=14 nm
 |technology=CMOS
@@ Line 27: / Line 30: @@
 |core count=10
 |thread count=20
+|max memory=768 GiB
 |max cpus=2
-|max memory=768 GiB
+|smp interconnect=UPI
+|smp interconnect links=2
+|smp interconnect rate=9.6 GT/s
 |tdp=85 W
-|package module 1={{packages/intel/fclga-3647}}
+|tcase min=0 °C
+|tcase max=77 °C
+|package name 1=intel,fclga_3647
 }}
-'''Xeon Silver 4114T''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114T, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
+'''Xeon Silver 4114T''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
 This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications.
 == Cache ==
-{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 {{cache size
 |l1 cache=640 KiB
@@ Line 172: / Line 180: @@
 == Frequencies ==
 {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
-{{frequency table}}
+{{frequency table
+|freq_base=2,200 MHz
+|freq_1=3,000 MHz
+|freq_2=3,000 MHz
+|freq_3=2,800 MHz
+|freq_4=2,800 MHz
+|freq_5=2,700 MHz
+|freq_6=2,700 MHz
+|freq_7=2,700 MHz
+|freq_8=2,700 MHz
+|freq_9=2,500 MHz
+|freq_10=2,500 MHz
+|freq_avx2_base=1,800 MHz
+|freq_avx2_1=2,900 MHz
+|freq_avx2_2=2,900 MHz
+|freq_avx2_3=2,700 MHz
+|freq_avx2_4=2,700 MHz
+|freq_avx2_5=2,300 MHz
+|freq_avx2_6=2,300 MHz
+|freq_avx2_7=2,300 MHz
+|freq_avx2_8=2,300 MHz
+|freq_avx2_9=2,200 MHz
+|freq_avx2_10=2,200 MHz
+|freq_avx512_base=1,100 MHz
+|freq_avx512_1=1,800 MHz
+|freq_avx512_2=1,800 MHz
+|freq_avx512_3=1,600 MHz
+|freq_avx512_4=1,600 MHz
+|freq_avx512_5=1,500 MHz
+|freq_avx512_6=1,500 MHz
+|freq_avx512_7=1,500 MHz
+|freq_avx512_8=1,500 MHz
+|freq_avx512_9=1,400 MHz
+|freq_avx512_10=1,400 MHz
+}}
+[[Category:microprocessor models by intel based on skylake low core count die]]

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4114T - Intel#io +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipset	Lewisburg +
clock multiplier	22 +
core count	10 +
core family	6 +
core name	Skylake SP +
core stepping	U0 +
designer	Intel +
family	Xeon Silver +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon silver/4114t +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ description	16-way set associative +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count	2 +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4114T +
name	Xeon Silver 4114T +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR3MM +
s-spec (qs)	QN7A +
series	4000 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2400 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	20 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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