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Difference between revisions of "intel/xeon gold/6146"
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{{intel title|Xeon Gold 6146}} | {{intel title|Xeon Gold 6146}} | ||
− | {{ | + | {{chip |
|name=Xeon Gold 6146 | |name=Xeon Gold 6146 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6146 | |model number=6146 | ||
+ | |s-spec qs=QN7C | ||
|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
|first launched=July 11, 2017 | |first launched=July 11, 2017 | ||
+ | |release price=$3286.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6100 |
|locked=Yes | |locked=Yes | ||
|frequency=3,200 MHz | |frequency=3,200 MHz | ||
Line 17: | Line 19: | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
|core name=Skylake SP | |core name=Skylake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=H0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 27: | Line 30: | ||
|core count=12 | |core count=12 | ||
|thread count=24 | |thread count=24 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=165 W | |tdp=165 W | ||
− | |package | + | |tcase min=0 °C |
+ | |tcase max=76 °C | ||
+ | |dts min=0 °C | ||
+ | |dts max=98 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |successor=Xeon Gold 6246 | ||
+ | |successor link=intel/xeon_gold/6246 | ||
+ | }} | ||
+ | '''Xeon Gold 6146''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a {{intel|turbo boost}} frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | The Xeon Gold 6146 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=12 MiB | ||
+ | |l2 break=12x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=24.75 MiB | ||
+ | |l3 break=18x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,200 MHz | ||
+ | |freq_1=4,200 MHz | ||
+ | |freq_2=4,200 MHz | ||
+ | |freq_3=4,100 MHz | ||
+ | |freq_4=4,100 MHz | ||
+ | |freq_5=4,000 MHz | ||
+ | |freq_6=4,000 MHz | ||
+ | |freq_7=4,000 MHz | ||
+ | |freq_8=4,000 MHz | ||
+ | |freq_9=3,900 MHz | ||
+ | |freq_10=3,900 MHz | ||
+ | |freq_11=3,900 MHz | ||
+ | |freq_12=3,900 MHz | ||
+ | |freq_avx2_base=2,600 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=3,300 MHz | ||
+ | |freq_avx2_10=3,300 MHz | ||
+ | |freq_avx2_11=3,300 MHz | ||
+ | |freq_avx2_12=3,300 MHz | ||
+ | |freq_avx512_base=2,100 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=3,100 MHz | ||
+ | |freq_avx512_6=3,100 MHz | ||
+ | |freq_avx512_7=3,100 MHz | ||
+ | |freq_avx512_8=3,100 MHz | ||
+ | |freq_avx512_9=2,700 MHz | ||
+ | |freq_avx512_10=2,700 MHz | ||
+ | |freq_avx512_11=2,700 MHz | ||
+ | |freq_avx512_12=2,700 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00122.html|test_timestamp=2017-10-13 22:51:29-0400|chip_count=2|core_count=24|thread_count=24|vendor=Cisco Systems|system=Cisco UCS C240 M5 (Intel Xeon Gold 6146, 3.20GHz)|SPECspeed2017_int_base=9.79|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00123.html|test_timestamp=2017-11-14 13:48:35-0500|chip_count=4|core_count=48|thread_count=48|vendor=Cisco Systems|system=Cisco UCS C480 M5 (Intel Xeon Gold 6146, 3.20GHz)|SPECspeed2017_int_base=9.88|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00198.html|test_timestamp=2017-10-13 08:37:48-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)|SPECspeed2017_fp_base=105|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00205.html|test_timestamp=2017-10-13 10:17:48-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)|SPECrate2017_int_base=163|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00209.html|test_timestamp=2017-10-13 05:59:56-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)|SPECspeed2017_int_base=9.7|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00212.html|test_timestamp=2017-10-13 14:38:34-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)|SPECrate2017_fp_base=169|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00402.html|test_timestamp=2017-10-24 06:12:20-0400|chip_count=2|core_count=24|thread_count=24|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)|SPECspeed2017_fp_base=106|SPECspeed2017_fp_peak=108}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00414.html|test_timestamp=2017-10-22 23:24:41-0400|chip_count=2|core_count=24|copies_count=48|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)|SPECrate2017_fp_base=168|SPECrate2017_fp_peak=171}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00419.html|test_timestamp=2017-10-23 13:24:47-0400|chip_count=2|core_count=24|copies_count=48|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)|SPECrate2017_int_base=159|SPECrate2017_int_peak=167}} | ||
}} | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:45, 29 December 2019
Edit Values | |
Xeon Gold 6146 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6146 |
S-Spec | QN7C (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $3286.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 3,200 MHz |
Turbo Frequency | 4,200 MHz (1 core) |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 165 W |
Tcase | 0 °C – 76 °C |
TDTS | 0 °C – 98 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6146 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a turbo boost frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6146 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
![]() |
Integrated Memory Controller
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Expansions[edit]
![]() |
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,200 MHz | 4,200 MHz | 4,200 MHz | 4,100 MHz | 4,100 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-13 22:51:29-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS C240 M5 (Intel Xeon Gold 6146, 3.20GHz)
Tested: 2017-10-13 22:51:29-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS C240 M5 (Intel Xeon Gold 6146, 3.20GHz)
SPECspeed2017_int_base: 9.79
Test: SPEC CPU2017
Tested: 2017-11-14 13:48:35-0500
Chips: 4, Cores: 48, Threads: 48
Vendor: Cisco Systems
System: Cisco UCS C480 M5 (Intel Xeon Gold 6146, 3.20GHz)
Tested: 2017-11-14 13:48:35-0500
Chips: 4, Cores: 48, Threads: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS C480 M5 (Intel Xeon Gold 6146, 3.20GHz)
SPECspeed2017_int_base: 9.88
Test: SPEC CPU2017
Tested: 2017-10-13 08:37:48-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
Tested: 2017-10-13 08:37:48-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
SPECspeed2017_fp_base: 105
Test: SPEC CPU2017
Tested: 2017-10-13 10:17:48-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
Tested: 2017-10-13 10:17:48-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
SPECrate2017_int_base: 163
Test: SPEC CPU2017
Tested: 2017-10-13 05:59:56-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
Tested: 2017-10-13 05:59:56-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
SPECspeed2017_int_base: 9.7
Test: SPEC CPU2017
Tested: 2017-10-13 14:38:34-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
Tested: 2017-10-13 14:38:34-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.20 GHz, Intel Xeon Gold 6146)
SPECrate2017_fp_base: 169
Test: SPEC CPU2017
Tested: 2017-10-24 06:12:20-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
Tested: 2017-10-24 06:12:20-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
SPECspeed2017_fp_base: 106
SPECspeed2017_fp_peak: 108
Test: SPEC CPU2017
Tested: 2017-10-22 23:24:41-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
Tested: 2017-10-22 23:24:41-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
SPECrate2017_fp_base: 168
SPECrate2017_fp_peak: 171
Test: SPEC CPU2017
Tested: 2017-10-23 13:24:47-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
Tested: 2017-10-23 13:24:47-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz)
SPECrate2017_int_base: 159
SPECrate2017_int_peak: 167
Facts about "Xeon Gold 6146 - Intel"