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Difference between revisions of "intel/xeon gold/5118"
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{{intel title|Xeon Gold 5118}}
 
{{intel title|Xeon Gold 5118}}
−
{{mpu
+
{{chip
 
|name=Xeon Gold 5118
 
|name=Xeon Gold 5118
 
|image=skylake sp (basic).png
 
|image=skylake sp (basic).png
Line 8: Line 8:
 
|part number=CD8067303536100
 
|part number=CD8067303536100
 
|s-spec=SR3GF
 
|s-spec=SR3GF
 +
|s-spec qs=QMXH
 
|market=Server
 
|market=Server
 
|first announced=July 11, 2017
 
|first announced=July 11, 2017
Line 13: Line 14:
 
|release price=$1273.00
 
|release price=$1273.00
 
|family=Xeon Gold
 
|family=Xeon Gold
−
|series=5000
+
|series=5100
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,300 MHz
 
|frequency=2,300 MHz
 
|turbo frequency1=3,200 MHz
 
|turbo frequency1=3,200 MHz
 
|clock multiplier=23
 
|clock multiplier=23
 +
|cpuid=0x50654
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
−
|microarch=Skylake
+
|microarch=Skylake (server)
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
Line 31: Line 33:
 
|core count=12
 
|core count=12
 
|thread count=24
 
|thread count=24
 +
|max memory=768 GiB
 
|max cpus=4
 
|max cpus=4
−
|max memory=768 GiB
+
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 
|tdp=105 W
 
|tdp=105 W
 
|tcase min=0 °C
 
|tcase min=0 °C
 
|tcase max=81 °C
 
|tcase max=81 °C
−
|package module 1={{packages/intel/fclga-3647}}
+
|dts min=0 °C
 +
|dts max=93 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Gold 5218
 +
|successor link=intel/xeon_gold/5218
 
}}
 
}}
−
'''Xeon Gold 5118''' is a {{arch|64}} [[dodeca-core]] [[x86]] server microprocessor set to be introduced by [[Intel]] in July 2017. This processor operates at 2.3 GHz.
+
'''Xeon Gold 5118''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
−
 
 
−
{{unknown features}}
 
−
 
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
 
|l1 cache=768 KiB
 
|l1 cache=768 KiB
Line 63: Line 69:
 
|l3 policy=write-back
 
|l3 policy=write-back
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=768 GiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=107.3 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|bandwidth hchan=107.3 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,300 MHz
 +
|freq_1=3,200 MHz
 +
|freq_2=3,200 MHz
 +
|freq_3=3,000 MHz
 +
|freq_4=3,000 MHz
 +
|freq_5=2,900 MHz
 +
|freq_6=2,900 MHz
 +
|freq_7=2,900 MHz
 +
|freq_8=2,900 MHz
 +
|freq_9=2,700 MHz
 +
|freq_10=2,700 MHz
 +
|freq_11=2,700 MHz
 +
|freq_12=2,700 MHz
 +
|freq_avx2_base=1,900 MHz
 +
|freq_avx2_1=3,100 MHz
 +
|freq_avx2_2=3,100 MHz
 +
|freq_avx2_3=2,900 MHz
 +
|freq_avx2_4=2,900 MHz
 +
|freq_avx2_5=2,600 MHz
 +
|freq_avx2_6=2,600 MHz
 +
|freq_avx2_7=2,600 MHz
 +
|freq_avx2_8=2,600 MHz
 +
|freq_avx2_9=2,300 MHz
 +
|freq_avx2_10=2,300 MHz
 +
|freq_avx2_11=2,300 MHz
 +
|freq_avx2_12=2,300 MHz
 +
|freq_avx512_base=1,200 MHz
 +
|freq_avx512_1=2,900 MHz
 +
|freq_avx512_2=2,900 MHz
 +
|freq_avx512_3=2,400 MHz
 +
|freq_avx512_4=2,400 MHz
 +
|freq_avx512_5=1,800 MHz
 +
|freq_avx512_6=1,800 MHz
 +
|freq_avx512_7=1,800 MHz
 +
|freq_avx512_8=1,800 MHz
 +
|freq_avx512_9=1,600 MHz
 +
|freq_avx512_10=1,600 MHz
 +
|freq_avx512_11=1,600 MHz
 +
|freq_avx512_12=1,600 MHz
 +
}}
 +
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00093.html|test_timestamp=2017-09-30 22:55:00-0400|chip_count=2|core_count=24|thread_count=24|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)|SPECspeed2017_fp_base=82.7|SPECspeed2017_fp_peak=83.8}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00102.html|test_timestamp=2017-09-30 17:05:03-0400|chip_count=2|core_count=24|thread_count=24|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)|SPECspeed2017_int_base=7.62|SPECspeed2017_int_peak=7.81}}
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake high core count die]]

Latest revision as of 22:43, 28 December 2019

Edit Values
Xeon Gold 5118
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5118
Part NumberCD8067303536100
S-SpecSR3GF
QMXH (QS)
MarketServer
IntroductionJuly 11, 2017 (announced)
July 11, 2017 (launched)
Release Price$1273.00
ShopAmazon
General Specs
FamilyXeon Gold
Series5100
LockedYes
Frequency2,300 MHz
Turbo Frequency3,200 MHz (1 core)
Clock multiplier23
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingM0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP105 W
Tcase0 °C – 81 °C
TDTS0 °C – 93 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 5118 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112
Normal2,300 MHz3,200 MHz3,200 MHz3,000 MHz3,000 MHz2,900 MHz2,900 MHz2,900 MHz2,900 MHz2,700 MHz2,700 MHz2,700 MHz2,700 MHz
AVX21,900 MHz3,100 MHz3,100 MHz2,900 MHz2,900 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz
AVX5121,200 MHz2,900 MHz2,900 MHz2,400 MHz2,400 MHz1,800 MHz1,800 MHz1,800 MHz1,800 MHz1,600 MHz1,600 MHz1,600 MHz1,600 MHz

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-09-30 22:55:00-0400
Chips: 2, Cores: 24, Threads: 24
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_fp_base: 82.7
SPECspeed2017_fp_peak: 83.8
Test: SPEC CPU2017
Tested: 2017-09-30 17:05:03-0400
Chips: 2, Cores: 24, Threads: 24
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_int_base: 7.62
SPECspeed2017_int_peak: 7.81
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5118&oldid=95111"
Facts about "Xeon Gold 5118 - Intel"
RDF feed
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +